The Diamond Series enables designers to achieve 10% to 40% lower code size compared to conventional RISC cores, depending on the actual code. Reducing code size results in higher performance, smaller memory sizes, and better power dissipation – key parameters in cost-sensitive, highly integrated SOC designs

Clock gating is a very effective power reduction technique that reduces power by stopping unnecessary clocking activity to parts of the logic that are not in use on a particular clock cycle. Tensilica has designed fine-grained clock gating for every functional element of these processors into the Diamond Standard Series. The Diamond Standard Series processor architecture dramatically lowers power consumption since it is designed to use power very efficiently. As an example, the Diamond 108Mini processor dissipates less than 60 µW/MHz in a representative 0.13 µm process technology.

You can buy Xtensa and/or Diamond Standard processors directly from our reseller partners. In addition, Tensilica partners with leading foundries and programmable logic suppliers to validate its RTL, design and implementation flows.

Reseller partners:

• Fujitsu
• Global Unichip (for TSMC)
• NEC
• SMIC

Silicon partners:

• Altera
• IBM
• TSMC
• UMC
• Xilinx