Wolfie.. I'm sure you posted this already, but here it is again...

SUPPLEMENTAL DECLARATION OF ALVIN M. DESPAIN

IN SUPPORT OF PLAINTIFFS' REPLY CLAIM CONSTRUCTION BRIEF

- 1 -

I, Alvin M. Despain, declare as follows:

DISPUTED TERMS

163. In Defendants' Brief Regarding Construction of Disputed Claim Terms of the 336

and 148 Patents, referred to herein as "Defendants' 336 Brief" for the portions of this declaration

addressing the '336 patent, Defendants have made several technical misstatements about the

Magar prior-art reference and the "varying together" limitations that I wish to clarify.

Disputed Terms: '336 Patent

Disputed Term: "An Entire Ring Oscillator Variable Speed System Clock in Said

Integrated Circuit"

164. This discussion applies to all four of the various iterations of this limitation that I

discuss in my first declaration at ¶¶ 44-64. As I did in that declaration, I will refer to "an entire

ring oscillator variable speed system clock in said integrated circuit" herein as "an entire ring

oscillator." See ¶ 44. Also, statements I make herein about "an entire ring oscillator" (claims 1-

5) are meant to apply to "an entire oscillator" (claims 6-9) and "an entire variable speed clock"

(claim 10) as well.

165. As I explained in my original declaration, Magar teaches the use of a traditional

crystal oscillator in conjunction with a clock generator circuit to provide internal timing signals.

The Magar crystal oscillator includes an off-chip crystal, connected between pins X1 and X2 of a

clock generator, where the crystal controls the frequency of the CPU clock. See Despain ¶ 49.

Referring to Exhibit I of the Declaration of David J. Lender, which is the Magar patent, you can

see the "Clock Gen" circuit at the right side of Fig. 2a, with its corresponding inputs X1 and X2

and quarter-cycle clock outputs Q1, Q2, Q3, Q4 and CLKOUT (i.e., the internal timing signals).

See Magar, Ex. I, 15:22-41.

166. What Magar does not explicitly show is the circuitry used to drive the external

crystal. For a crystal to vibrate, an alternating input must be provided to that crystal. In most

crystal oscillators, an inverting and amplifying circuit (which I will refer to herein as the "drive

circuit") provides this alternating input. Some of the frequencies of this signal will be at the

resonant frequency of the crystal, so the crystal will start oscillating in synchrony with those

 

- 2 -

portions of the signal, while effectively filtering out other portions of the signal at other

frequencies. Because the drive circuit is also an amplifier, it amplifies the signal coming out of

the crystal. The now-amplified output of the drive circuit is fed back into the crystal as an input,

in a process known as "feedback." The result is that the frequencies that are near the resonant

frequency of the crystal will be amplified and sustained as an oscillating output, while other

frequencies of the signal will die away. The prosecution history notes that this feature of crystals

is the main reason for their use as crystal oscillators (where a "crystal oscillator" is the crystal

plus its drive circuitry):

The single, fixed, oscillation frequency of the crystal is determined

by how the device is manufactured, i.e., how the crystal is cut and

trimmed, and other factors. Crystals are used precisely for this

purpose; they oscillate at a given frequency within a tolerance

determined by their manufacture.

Amd. 7/3/97 at 4, Ex. 8.

167. Magar does not explicitly teach the crystal drive circuit, but, as I described, a

crystal will not provide a sustained alternating output without such a circuit. There is no

indication or reason that the drive circuit would be a part of the "clock gen" circuit of Magar,

which "produces the various required timing signals needed of the CPU." Amd. 2/6/98 at 4, Ex.

9. Because the output of the Magar clock generator circuit is described as "four quarter-cycle

clocks Q1 to Q4" and CLKOUT (which has the same period as Q1), I believe that it is likely that

the clock generator circuit is just a divider circuit. Magar, Ex. I, 15:34-40. As such, Magar is not

clear where the drive circuitry is located, but the applicants' attorney assumed (correctly, I think)

that it would likely be on-chip: "The crystal might be connected directly to two pins on the CPU,

as in Magar, and be caused to oscillate by circuitry contained in the CPU with the aid of possibly

other external components." Amd. 7/3/97 at 4, Ex. 8. Applicants' attorney also highlighted

another reference where he assumed the drive circuit (which he referred to in this instance as

"oscillator circuitry") was off-chip, because the clock input was provided through a single pin:

"Alternatively, the crystal may be contained in a package with the oscillation circuitry, the

packaged component thus called an oscillator, and connected to one pin on the CPU as in

Edwards et al., U.S. Patent 4,680,698." Id. Edwards does not teach what the source of the clock

 

- 3 -

signal through the single clock pin would be (i.e., it never mentions the word "crystal"), but

applicants' attorney assumed it could work with an off-chip crystal packaged together with its

drive circuitry as a discrete crystal oscillator, as his statement demonstrates.

168. Defendants make statements about Magar in their 336 Brief that are inaccurate

and misleading. Specifically, Defendants claim that the crystal in Magar "serves as a reference

signal for the clock generator to lock onto. See Gafford Decl. ¶ 25." Defendants' 336 Brief at 7

(emphasis added). Yet, a "reference signal" and the concept of "locking" are specific technical

terms with specific meanings, and have nothing at all to do with the clock generator and external

crystal of Magar. For example, in my original declaration, I explained how a DLL delay-"locks"

an internal clock signal onto an external "reference signal" using offsetting delay. Despain ¶ 51.

This locking typically involves the use of a comparator, which is a circuit element that receives

two different inputs (like a reference signal and a second signal), determines the difference

between their values, and outputs that difference as a signal. This output signal of the

comparator can be used to do different things, like to determine an offsetting delay in

conjunction with a DLL. The output signal of the comparator can also be used in conjunction

with a feedback loop to adjust the second signal until it is close in value in frequency or phase

(e.g.) to the reference signal, thereby frequency- or phase-locking the two signals. The key point

is that none of this functionality is taught in Magar. Tellingly, Mr. Gafford agrees, as he never

describes Magar as teaching a reference signal or locking functionality, contrary to Defendants'

cite of his declaration for this proposition. Instead, Mr. Gafford merely notes that the external

crystal of Magar "controls" the frequency of the clock generator, and is therefore the "dominant

influence" on the frequency of the clock generator. Gafford ¶ 25.

169. Defendants similarly claim that the applicants distinguished over prior art chips in

which an off-chip crystal is used as a "reference signal" for the on-chip clock circuitry.

Defendants' 336 Brief at 12-13 (emphasis added). They quote applicants' attorney's statements

referring to the Edwards patent, discussed above, as well as two additional references, Palmer

and Pohlman et al. See Amd. 7/3/97 at 4, Ex. 8. But as described above, Edwards does not teach

an oscillator of any kind, and the applicants' attorney described the teachings of the other two

 

- 4 -

references as "systems [that] operate at a frequency determined by the external crystal," i.e.,

conventional crystal oscillators. Id.; Defendants' 336 Brief at 12. Because these references

disclose traditional crystal oscillators, they are no different in this regard than Magar, and in no

way teach a reference signal, second signal, comparator, or delay / frequency / phase locking

functionality.

Disputed Terms: "Varying Together / Vary Together / Varying … in the Same Way /

Varying in the Same Way"

170. As in my first declaration, I will refer to the different iterations of these

limitations as the "vary together" limitations. Despain ¶ 65.

171. In their Brief, Defendants claim that an increase in the CPU frequency capability

of 50 MHz and an increase in the clock rate of the ring oscillator of 1 MHz "could not possibly

constitute 'varying together' - the two are not in harmony." Defendants' 336 Brief at 22. I

disagree. One of ordinary skill in the art appreciates that not only are changes of this magnitude

perfectly acceptable in the context of the invention of the '336 patent, but also may actually occur

depending on the operating frequencies involved. For example, if the actual speed of the CPU

and the ring oscillator is in the 1 GHz (i.e., 1000 MHz) range, a variation of 50 MHz is only 5%

and a variation of 1 MHz is only 0.1%. I believe variations in the processing frequency

capability of the CPU and the speed of the ring oscillator could easily be +/- 5% under typical

operating conditions for a 1 GHz or faster microprocessor. It is not the magnitude of the

difference between the changes in the parameters of the CPU and the ring oscillator that is

important, but rather that the changes in these parameters occur in the same direction − i.e., both

increase or both decrease.

172. Defendants and Mr. Gafford assert that if the only requirement for the "varying

together" limitations is that they both increase or both decrease, it is possible for the clock rate of

the ring oscillator to exceed the maximum theoretical performance (i.e., upper end of the

processing frequency capability range), in which case the CPU would cease to provide a valid

output. Gafford ¶ 21; Defendants' 336 Brief at 23. I agree that if this crossover occurs, the CPU

would not function correctly. This is shown in Mr. Gaffords' graph in ¶ 21 of his declaration

 

- 5 -

when the blue line ("on-chip clock frequency") crosses over and above the green line ("CPU

processing frequency"). However, this crossover point will never occur if a person of ordinary

skill follows the teachings of the '336 patent, because if he or she wishes to run the CPU at the

maximum theoretical performance, "CPU 70 will always execute at the maximum frequency

possible, but never too fast." '336, 17:1-2. This is because the speed of the ring oscillator and

the processing frequency capability of the CPU vary together, as they are on the same integrated

circuit substrate. See, e.g., '336, 17:1-10.

173. The graph Defendants provide in their Brief for their interpretation of the "vary

together" limitations (Defendants' 336 Brief at 23) is a perfect illustration of why a person of

ordinary skill would never expect that changes in speed or propagation delays would be exactly

matched between the CPU and ring oscillator. See Despain ¶¶ 70-73. Defendants' two perfectly

straight lines with identical slopes for the clock rate of the ring oscillator (blue), and the

processing frequency capability of the CPU (green), which exactly parallel each other but are

slightly offset, do not resemble the operation of any real-world device. In reality, microvariations

in voltage and temperature and manufacturing guarantee that these parameters will

diverge at various points on the graph. Defendants' rigid abstraction is not representative of the

operation of any actual device, but does serve to graphically demonstrate why their construction

is inconsistent with the view of a person of ordinary skill in the art.

174. If the definition for "vary together" was "increasing or decreasing

commensurately," a person of ordinary skill would not know how to practice (or avoid

practicing) this limitation. "Commensurately" is not a technical term, and a person of ordinary

skill would not know how to quantify this requirement. For example, Defendants' 336 Brief on

pages 22-23 suggests that a 50:1 ratio of varying together would not qualify (irrespective of what

percent of the actual operating speed this constitutes), but would a 20 to 1 ratio qualify? How

about 10 to 1 ratio? Or something that is not an integer relationship, like 2.5 to 1? What if the

ratio changes, from 3:1 to 2:1 − would this qualify? These issues are avoided by Plaintiffs'

proposed definition, which only requires that the parameters both increase or both decrease.

 

- 6 -

Disputed Terms: '584 Patent

Disputed Term: "Instruction Groups"

175. I previously stated that I believe that instruction groups do not require rightjustified

operands. Despain ¶ 116. As I stated, many of the instructions described in the file

history and covered by claim 29 will provide the claimed behavior even if operands are not

always right-justified. To make my position and its basis absolutely clear, I will elaborate on this

point.

176. First, instructions such as SKIP and MICROLOOP obviously do not include an

operand at all. Thus, it is self-evident that either of these instructions will provide the claimed

behavior of "caus[ing] an access to an … instruction [that is] located at a predetermined position

from a boundary of said instruction groups," regardless of where operands might be located

within any instruction groups.

177. To elucidate further, SKIP causes an access to the first instruction in the next

group. '584, 14:20-24. The SKIP instruction does not use any immediate operand, and its target

is predetermined (always the first instruction in the next group). SKIP may use non-immediate

operands, e.g., to test for various conditions as described at '584, 23:15-66, but such operands are

not in the instruction register. For instance, SKIP-IF-ZERO tests the top item of the parameter

stack ('584, 23:19-31), SKIP-IF-NO-CARRY tests the processor's carry flag ('584, 23:39-45),

and so on. Thus, the positioning of operands in the instruction register will not affect the

behavior of the SKIP instruction at all.

178. Similarly, MICROLOOP causes execution to return to the first instruction in the

accessing group. '584, 14:41-57. Like SKIP, MICROLOOP does not use any immediate

operand; its target is predetermined (always the first instruction in the accessing group).

MICROLOOP may use non-immediate operands, e.g., to test for various conditions as described

at '584, 24:39-25:19, but such operands are not in the instruction register. For instance, ULOOPUNTIL-

DONE tests and decrements a loop counter stored in a special register (LOOP

COUNTER 92 of '584, Fig. 2; see '584, 24:39-43), ULOOP-IF-ZERO tests the top item of the

parameter stack ('584, 24:44-49), and so on. Thus, as with SKIP, the positioning of operands in

 

- 7 -

the instruction register will not affect the behavior of the SKIP instruction at all.

179. The lack of effect of operand position on SKIP and MICROLOOP holds

regardless of how the bits of the target instruction group are arranged in the instruction register.

This can be understood by distinguishing two aspects of processor design: semantics and

implementation. Semantics refers to the behavior, i.e., the effect of executing an instruction.

Implementation refers to the specific hardware details by which that behavior is made to occur.

Thus, for example, the existence of a SKIP instruction that jumps to the first instruction of the

next instruction group is semantics, while the clearing of a microcode counter in conjunction

with a fetch of the next instruction group ('584, 14:24-27) is implementation.

180. The semantics of SKIP and MICROLOOP do not limit the targets of these

instructions to any particular type of instruction. Thus, the target of a SKIP or MICROLOOP

might or might not use an immediate operand; the semantics of whatever instruction happens to

be the target will determine whether it uses an immediate operand. Thus, the presence or

absence of an operand, let alone its position in the instruction register, has no relevance to SKIP

or MICROLOOP. Since claim 29 is intended to cover either of these instructions, limiting the

claim to cases where "any operand that is present must be right-justified" is unwarranted.

181. Further, I do not believe that any universal restrictions on where an operand can

be located within a group is warranted by either the claims or the file history. Claim 29 states

that "certain of said instruction groups include at least one instruction that, when executed,

causes an access to an operand or instruction or both, said operand or instruction being located at

a predetermined position from a boundary of said instruction groups." Thus, to the extent that

"located at a predetermined position from a boundary" constrains the location of operands it does

so for instructions in "certain of said instruction groups," not necessarily for all instruction

groups or all instructions.

182. I have also observed that during prosecution, claim 97 of the application, which

eventually issued as claim 29 of the '584 patent, was amended to remove any requirement of

selecting an operand. Specifically, as originally filed, claim 97 recited a step of "selecting, in

accordance with position in said instruction register of one of said instructions of one of said

 

- 8 -

instruction groups, an operand from said one of said instruction groups for use by said central

processing unit." Amd. 4/8/96 at 8, Ex. 13. This was later changed to "selecting an operand

from said one of said instruction groups for use by said central processing unit" (Amd. 6/12/97 at

7, Ex. 14) before being dropped altogether, in favor of the final claim language. Thus, claim 29

refers to "supplying … said operand or instruction or both to said central processing unit." '584,

34:63-65. Supplying an operand is not required, as the claim can also be met by supplying an

instruction.

183. Further, even assuming that some restriction on operand alignment in at least

some of the groups is appropriate, limiting to "right-justified" operands unduly limits the claim.

With respect to operand alignment, the specification states that the advantage of the disclosed

alignment of variable-width operands is "the saving of a number of opcodes required to specify

the different operand sizes in other microprocessors." '584, 16:24-26. The file history describes

how aligning the operands "always in the same place within an instruction group" solves the

problem of having to "take those bits and then move them some amount to the right to align the

least significant operand bit with the lowest bit on the CPU internal data bus." Amd. 6/12/97 at

9-10, Ex. 14.

184. Those skilled in the art would have immediately recognized that right-justifying

the operand is not the only way to provide operands "always in the same place within an

instruction group". The CPU internal data bus includes wiring that connects the instruction

register to the data registers of the CPU. An example is the "internal data bus" labeled 90 in Fig.

2 of the '584 patent, which connects (among other things) instruction register 108 and parameter

stack 74. Right justifying the operands allows specific wires of the CPU data bus to connect to

specific bit positions in the instruction register without the need for shift circuits and associated

logic to apply variable shifts, as applicants explained during prosecution.

185. But right-justifying the operand in the instruction register is not the only way to

avoid shift circuits and associated logic. As long as the operands are at a fixed position within

the register, wires can be correctly connected between bit positions in the instruction register and

bit positions in the data register, without need for shift circuits or the associated logic. For

 

CERTIFICATE OF SERVICE

I hereby certify that counsel of record who are deemed to have consented to electronic

service are being served this 9th day of April, 2007, with a copy of this document via the Court’s

CM/ECF system per Local Rule CV-5(a)(3). Any other counsel of record will be served by

electronic mail, facsimile transmission and/or first class mail on this same date.

/s/ Roger L. Cook ______

Roger L. Cook