Quote from Phillip Brooks:

 "The ‘584 patent addresses a bottleneck problem where the computing speed of the microprocessor depends on how quickly instructions can be loaded from memory into the instruction register of the microprocessor."

The problem lies with how the term "Instruction Groups" was originally intended from the applicant (Us)

Unfortunately you'll have to read all of this from theclaim construction ruling:

3. ‘584 Patent

a. “microprocessor”

The Court adopts its previous construction of this term in the ‘336 patent. See Section IV(B)(1)(b).

b. “central processing unit”

The Court adopts its previous construction of this term in the ‘336 patent. See Section IV(B)(1)(a).

c. “instruction groups”

The next term is “instruction groups.” The plaintiffs’ proposed construction is “sets of from 1 to a maximum number of sequential instructions, each set being provided to the instruction register as a unit and having a boundary.” The defendants propose “sets of from 1 to a maximum number of sequential instructions, in which the execution of the instruction depends on each set being provided to the instruction register as a unit and in which any operand that is present must be right justified and which cannot encompass a single 32-bit traditional conventional instructiongrou.” The dispute is whether an operand that is present in the instruction group must be right justified and whether the instruction p may encompass a single 32-bit traditional conventional instruction. The plaintiffs contend that right justified operands are a feature of the preferred embodiment. The plaintiffs also argue that the claim language was broadened during prosecution history when the language “selecting, in accordance with position in said instruction register of one of said instructions of one of said instruction groups, an operand from said one of said instruction groups” was removed from the claim. Amendment, June 12, 1997, at 6. In addition, the plaintiffs point out that the specification includes 32-bit instructions. See ‘584 patent, 20:41-42. The defendants argue that the specification states that “operands must be right justified in the instruction register.” ‘584 patent, 16:15-16. In addition, the defendants argue that the applicants limited operands in this manner to overcome prior art rejections. See Amendment, June 17, 1997, at 13; Amendment, February 5, 1998, at 7. The defendants also contend that although the specification includes 32-bit instructions, the specification never identifies a single 32-bit instruction as instruction groups. According to the defendants, the specification defines “instruction group” as “being 8-bit and 16 or 24-bit instructions.” ‘584 patent, 23:4-7. The specification and prosecution history refer to the fact that operands in the instruction register must be right justified. The applicants, however, did not exclude a single 32-bit instruction as an instruction group. In a preferred embodiment, a microprocessor fetches instructions “in 32-bit chunks called 4-byte instruction groups” where an “instruction group may contain from one to four instructions.” ‘584 patent, 23:4-5, 19:18-19. If a 4-byte (or 32-bit) instruction group contains one instruction, then the instruction group may contain a single 32-bit instruction. The Court construes “instruction groups” to mean “sets of from 1 to a maximum number of sequential instructions, each set being provided to the instruction register as a unit and having a boundary, and in which any

operand that is present must be right justified.”