ease,

It sounds like you have a fundamental misunderstanding of how PLL circuits are used in modern microprocessors.

Sure, clock skew can be an issue if you transmit the clock signal across long distances, such as across an entire motherboard or several feet of wiring. However, clock skew is less of an issue if you are only transmitting a few millimeters from one side of the chip to the other. Also, PLL circuits ADD clock jitter (noise); they do not correct it. These were the issues discussed in the Intel presentation that you referenced.

In contrast, in modern microprocessors, PLL circuits are used as "clock multipliers" so that the CPU clock frequency is frequency and phase locked to a fixed multiple of the external crystal (or external clock) frequency, e.g., PLL frequency = external crystal frequency x 2.0. In more sophisticated microprocessors, the "multiplier" can be programmed by the IC vendor/user/operating system usually in steps of 0.5, e.g. 2.0, 2.5, 3.0, 3.5, etc. Based on TPL's claim charts supplied in the '336 re-exam, it is these PLL-based "clock multipliers" that TPL is accusing of infringing the '336 patent.

The problems TPL/PTSC face are:

(a) The external crystal/clock generator is an essential part of PLL-based clocks, where the clock will not function/oscillate properly without an external crystal/clock generator. Therefore, PLL-based clocks are not "entirely" on-chip;

(b) The CPU clock frequency is frequency and phase locked to a fixed multiple of the external crystal/clock generator. If you increase/decrease the frequency of the external crystal/clock generator by a factor of 2.01952, you also increase/decrease the clock frequency by a factor of 2.01952. Therefore, PLL-based clocks "directly rely" on an external crystal/clock generator to generate the clock signal;

(c) If the multiplier of the PLL circuit can be programmed by the IC vendor/user/operating system, then the clock would also "directly rely" on a "command input control signal" to generate the clock signal; and

(d) Using PLL-based circuits as "clock multipliers" is not new. See, for example, the InMOS transputer T414, Talbot, and McDermott references cited in '336 re-exam. The InMOS transputer reference seems particularly interesting since the inventors acknowledge that they knew about this device (e.g., it is briefly mentioned in the body of the '336 patent), yet the information was not disclosed to the patent examiner during the original examination. The Talbot reference is also owned by InMOS and appears to more particularly describe the PLL-based clock multiplier circuit used in the InMOS T414. Because the PLL-based clock is the most blatantly obvious feature of the InMOS transputer, these issues will be difficult for the inventors to explain, e.g. the inventors committed fraud for failing to disclose material information, or they did not disclose the information because the claims do not cover PLL-based clocks.