Fabricating for Low Power

Creating a hybrid design like the StrongARM isn't as simple as gluing together two architectures as disparate as the Alpha and the ARM. To attain the desired clock speeds, engineers from both companies worked together to redesign the whole data-path and cache structure of the CPU. Nevertheless, Digital's leading-edge fabrication process is ultimately what permits the StrongARM to run four times faster than previous ARM chips. The architectural changes exploit the speed of this silicon.

Digital's newest fabrication plant uses a next-generation process called CMOS-6, the same process Digital uses for its Alpha 21164A, which will exceed 350 MHz. It's a 0.35-micron, four-layer-metal CMOS process that yields high-speed, low-voltage transistors, thanks to extremely thin oxide insulation layers only 65 angstroms deep. Ultimately, this process will yield transistors that run at 0.9 V.

Low voltage is a crucial design point because power consumption varies with the square of the voltage. A chip fabricated on the 2-V CMOS-6 process will cons ume only 37 percent as much power as a chip fabricated on a comparable 3.3-V process. At 1.5 V, the power consumption is only 21 percent as much. The small feature size also reduces capacitance, saving even more power.

The actual die size will depend on how much cache memory is on the chip. Although this hasn't been announced, the first StrongARMs will probably have 32 KB of primary cache. By any measure, however, the StrongARM core is tiny -- a mere 115,000 transistors, compared to 3.3 million on a Pentium. Digital and ARM say their goal is to achieve performance of at least 300 million instructions per second per watt, at a cost of about 35 cents per MIPS. The first StrongARM chips are expected to consume around 500 milliwatts (less than half that consumed by a PowerPC 603).

In the consumer-electronics market, it's not sufficient just to have the cheapest CPU. The peripheral chips -- such as memory and graphics -- must be cheap, too. Very few low-voltage peripheral chips are available today, so the Strong-ARM is designed to work with regular 3.3-V components. This was a tough bullet to bite because it requires two different voltages on the same silicon, with separate sets of power rails and the attendant problems of eliminating noise and current leakage.

To further trim costs, the engineers designed the StrongARM's system interface so it can be either 32 or 64 bits wide. System designers can synchronize the interface to the CPU core (at fractional speeds ranging from one-half to one-ninth the core frequency) or to an external clock as fast as 66 MHz.

An even more radical design twist is that the circuits use edge-triggered latches with conditional clocks, instead of the more common level-triggered latches. This means the StrongARM inputs the clock signal into a section of logic only when that section is needed, so a function unit consumes power only when used. To go along with this, a new instruction stops all the internal clocks until they're awakened by an interrupt. These features sho uld make it easier to implement energy-saving sleep modes.

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