..336 emphases with first image highlighting the clock system....however, complete explanations in detail of the complete Sh-Boom processor(main CPU with register configuration and 8bit management through second DMA CPU )of the Sh-Boom are contributed first...with crystal clock...

Then leading into a completely separate processor issue,(no name processor) utilizing the DMA CPU( with traditional DMA controller ) in combination with embedded core clock timing / external bus crystal clock timing and the DRAM....all within the same sub straight....giving direct memory access....then leveraging the structure of DRAM with column latch architecture....calling it a monolithic computer complete with memory rendering it low cost and physically compact. IMO..the process is cumulative.

Was it a last min thought to incorporate this scheme ? There had to be some thought process going into the handshake sequence between the internal and external bus clocking and hand off between the two separate clock issues.

Doesn`t appear to be a last minute thing to me....Maybe he did maybe he didn`t....he had to be working the idea for some time making notes as he went along....not last minute....as read between noted conversations of Higgins and Fish.

doni