To all Newbies (A must read) DECLARATION OF ALVIN M. DESPAIN IN SUPPORT OF PLAINTIFFS' CLAIM CONSTRUCTION BRIEF.

UNITED STATES DISTRICT COURT EASTERN DISTRICT OF TEXAS
MARSHALL DIVISION
Technology Properties Limited and Patriot
Scientific Corporation,
Plaintiffs,
v.
Matsushita Electrical Industrial Co., Ltd.,
Panasonic Corporation of North America, JVC
Americas Corporation, NEC Corporation, NEC
Electronics America, Inc., NEC Corporation of
America, NEC Display Solutions of America,
Inc., NEC Unified Solutions, Inc., Toshiba
Corporation, Toshiba America, Inc., Toshiba
America Electronic Components, Inc., Toshiba
America Information Systems, Inc. and Toshiba
America Consumer Products, LLC,
Defendants.
(WARD)(JURY)

DECLARATION OF ALVIN M. DESPAIN IN SUPPORT OF PLAINTIFFS' CLAIM CONSTRUCTION BRIEF.

I, Alvin M. Despain, declare as follows:
Biography
1. I have worked in various areas of electrical engineering and computer science since 1957, when I started with the Southern California Edison Company in Los Angeles, California, as an Electrical Engineer Trainee. I have been a professor of electrical engineering and/or computer science since 1966 at the University of Utah, Utah State University, Stanford University, and the University of California at Berkeley. Currently I am Emeritus Professor of Electrical Engineering at the University of Southern California.
2. I received a Bachelor of Science degree in 1960, a Master of Science degree in 1964, and a PhD in 1966, all from the University of Utah.
3. I have conducted research, with my graduate students and colleagues, on computer systems for more than 40 years. I have supervised 33 PhD students (as chairman of the
students’ PhD supervisory committee), and an additional number of Master’s degree students.
4. I have published (usually with co-authors) more than 150 technical papers, two of which have won prizes.
5. I have co-founded four computer technology companies: Logan Engineering Products Company (LEPCO), Computer Information Systems, Xenologic, and Acorn Technologies. I have been a consultant to a number of other technology companies and to the
U.S. Government for more than 35 years.
6. I am the sole or lead inventor on seven issued U. S. patents and two additional published patent applications.
7. I am a lifetime fellow of the Institute of Electrical and Electronics Engineers (“IEEE”), awarded for my work in computer system architecture.
8. I have served as a consultant/expert witness for seven law firms in ten patent/ technology lawsuits.
Task
9. I was retained by the law firm of Townsend and Townsend and Crew LLP ("Townsend";), counsel to Plaintiffs Technology Properties Limited ("TPL") and Patriot Scientific Corporation ("Patriot") in January 2007. I was asked by Townsend to review the following U.S. Patents: 5,809,336 ("the '336 patent"), 6,598,148 ("the '148 patent"), and 5,4784,584 ("the '584 patent"). The patents are respectively attached to the Declaration of Roger L. Cook as Exhibits 1, 2 and 3. Collectively, I refer to these patents as the Moore Microprocessor Patents (“MMP”), and specifically as the "MMP patents-in-suit." I was asked to assist in determining the meaning of the claim terms of the MMP patents-in-suit. Methodology
10. The first step in the course of my analysis was to read the MMP patents-in-suit. I then reviewed their file histories, including the cited prior art. At times, I also referred to dictionaries and computer architecture books from the 1989 time frame (as well as both earlier and later) to confirm the ordinary meaning of some of the terms.
11. I reviewed the claim interpretations of NEC Corporation, NEC Corporation of America, NEC Display Systems of America, Inc., NEC Electronics America, Inc., and NEC Unified Solutions, Inc. (collectively, the "NEC Defendants"), as set forth in the January 18, 2007, letter from John Feldhaus to Roger Cook and Charles Hoge. I also reviewed the claim interpretations of Matsushita Electric Industrial, Ltd., Panasonic Corporation of North America, and JVC Americas Corp. (collectively, the "MEI Defendants"), as set forth in "Defendants Matsushita Electric Industrial, Ltd., Panasonic Corporation of North America and JVC Americas Corp.'s Patent Local Rule 4-2 Disclosure." I also reviewed the claim interpretations of Toshiba Corporation, Toshiba America, Inc., Toshiba America Electronic Components, Inc., Toshiba Information Systems, Inc., and Toshiba America Consumer Products, LLC (collectively, the "Toshiba Defendants"), as set forth in the January 18, 2007, letter from Michael Hawes to Roger Cook and Charles Hoge. Finally, I reviewed the claim interpretations of ARM, Inc., and ARM, Ltd., (collectively, the "ARM Defendants"), as set forth in the January 18, 2007, letter from Kevin Anderson to Roger Cook and Charles Hoge.
12. I reviewed the Joint Claim Construction Statement and Prehearing Statement that was filed on February 16, 2007. In Exhibit C of this document, the Defendants present their definitions for the claim terms. It is this document, referred to herein as "Defendants' Proposed Claim Constructions," that I used to consider and analyze the joint proposed claim constructions of the Defendants. Claim Meaning
13. In determining the meaning of the claims, I relied on the patents themselves, their file histories, the prior art cited in the patents, and the ordinary meaning of the claim terms at the time of the effective filing date of the patent applications. My analysis was done from the perspective of a person of ordinary skill in the art of the patents at the time of the inventions, which I have assumed is August 1989. 14. I have read and reviewed the meaning of the claims as set forth in Exhibit B of the Joint Claim Construction Statement and Prehearing Statement that was filed on February 16, 2007. I understand this chart to be Plaintiffs' proposed claim constructions ("Plaintiffs' Proposed Claim Constructions"). I agree with the claim constructions set forth in this document.
15. In reviewing Plaintiffs' Proposed Claim Constructions and Defendants' Proposed Claim Constructions, one of my purposes was to compare the parties' definitions to determine the extent to which Defendants, on the one hand, and Plaintiffs, on the other, agreed or disagreed on the meaning of the words and limitations of the claims.
16. For some terms and limitations, there is substantial agreement between the parties. (My references to "party" or "parties" reflect the two sides in this litigation.) However, there are instances where there is clear disagreement. Additionally, there are places where one party or the other chose not to interpret a term or limitation.
17. For the purpose of my analysis, in cases where both parties interpreted a term or limitation, and where there was substantial agreement between the parties, I reviewed those interpretations, and, based on my independent analysis, I concurred that a person of ordinary skill in the art would also interpret those terms similarly. I do not report on the terms on which there is substantial agreement between the parties.
18. In cases where both parties interpreted a term or limitation, but where there was not substantial agreement, I analyzed the each party's interpretation and support for the meanings that it chose.
19. Based on this analysis, and my understanding of how the term or limitation would be interpreted by a person of ordinary skill in the art at the time of the invention, I have determined that the claim constructions set forth in the Plaintiffs' Proposed Claim Constructions are the correct interpretations. FIELD OF THE MMP PATENTS-IN-SUIT
20. The MMP patents-in-suit relate to a high-performance microprocessor system. In particular, the MMP patents provide innovations in the areas of microprocessor clocking,
microprocessor instructions, and microprocessor memory.
'336 Patent
21. Modern microprocessors have millions or even hundreds of millions of transistors, which together conduct countless logical functions, each of which has to be precisely coordinated with the others so as to avoid a collision in operations. An analogy is the conductor of a symphony. If the conductor does not provide a timing reference for the beat of the music by waving a conducting baton, then the result will not be highly-coordinated symphonic music, but a cacophony. Similarly, a microprocessor needs its own timing reference, which is usually provided as a clock signal. A clock signal is generally a sinusoidal or square wave that is regularly varying, and which provides a rising or falling edge from which the central processing unit ("CPU") can derive its own "beat." The speed of the modern microprocessor is much faster than a conductor could ever wave a baton, however − generally on the order of millions or even billions of cycles a second. There are many different sources of clock signals − e.g., quartz crystal oscillators, voltage- and current-controlled oscillators, and ring oscillators. They are all similar in that they provide an alternating output.
22. One function that microprocessor systems use a clocking mechanism for is to coordinate moving data into and out of the microprocessor. This data typically moves into and out of the microprocessor through an input/output interface, which is the microprocessor's means to communicate with the outside world. The data rate itself may be based on a clock signal that is much slower than the system clock signal that is timing the operation of the CPU. Prior to the invention of the '336 patent, the system clock would have to be synchronous with the slower input/output clock, slowing all operations of the microprocessor. The '336 patent teaches a technique o "decouple" the slower input/output clock from the system clock, allowing them to run independently and therefore for the system clock to run faster.
23. Prior to the invention of the '336 patent, the source of the system clock signal in a microprocessor system was typically an off-chip crystal, which generally has a fixed frequency. In contrast, the '336 patent teaches the use of a variable-speed oscillator circuit to provide a system clock that is on the same chip as the microprocessor, and which is therefore subject to the same variations in operating conditions, such as temperature and voltage, and in manufacturing processes. As a result, these variations affect both the on-chip oscillator circuit and the microprocessor, causing the speed of the oscillator and the range of speeds the microprocessor can operate at to vary together, ensuring that the output of the microprocessor remains valid.
24. In common parlance, the term "clock" has multiple uses, as a noun, adjective, and verb. For instance, one may speak of a "wall clock"; (noun), a "clock signal" (adjective), or "clocking a racehorse" (verb). Similarly, in the field of electronic circuit design, the term "clock" is used in multiple ways, such as "a clock signal" (an electrical signal used for timing) or a "clock circuit" (a circuit that generates electrical signals used for timing). Electrical engineers
of ordinary skill in the art use the noun "clock" to describe both a clock signal and a clock circuit, and to those of ordinary skill in the art, which is meant is clear from the larger context in which the term is used.
25. The specification of the '336 patent follows this convention with regard to the use of the noun "clock." In some places the noun "clock" refers to a signal, and in other places to the circuit. It is always clear from the context whether a particular occurrence of the term refers to a signal or a circuit. The specification of the '336 patent also occasionally uses the verb "to clock"; to describe the action of providing a timing signal to a circuit or circuit component.
26. Rather than relying on a larger context as electrical engineers customarily do, I will endeavor to use the term "clock circuit" and "clock signal" as appropriate in different contexts.
'148 Patent
27. The '148 patent generally relates to a microprocessor that includes both a processing unit and memory on the same substrate. Providing the processing unit on the same substrate as the memory provides a significant performance benefit. A processing unit functions by interpreting and executing programmed instructions that are stored in memory. The instructions typically cause the processing unit to perform some operation on data, such as adding or multiplying data. The data that the processing unit performs the operation on is obtained from memory, and the result is sent to memory. In order to read data from or write data to memory, the processor must send an address to the memory that provides the location of the data in memory. The path over which the processing unit and the memory communicate is called a bus. The speed at which information travels over this bus greatly impacts the performance of an electronic device such as a computer.
28. The '148 patent teaches increasing this speed by providing the processing unit and the memory on the same substr ate. By providing memory on the same substrate as the processing unit, a direct path is provided between the memory and the processing unit. In the '148 patent, the memory occupies a majority of the active area of the substrate. The active area refers to the portion of the substrate that includes active circuitry.
29. The memory stores both instructions and data that are used by the processing unit. There are many different types of memory. Different examples include dynamic random access memory ("DRAM"), registers, cache, and latches. These different types of memory vary in their architecture and performance. For example, DRAM is made up of certain arrangements of capacitors and transistors. Registers and cache, on the other hand, typically are implemented as static random access memory ("SRAM") that contains only transistors. Latches are often made up of flip-flops, which also contain only transistors but in a different configuration than in SRAM. Because of these differences in architecture, latches typically are faster than registers and cache, which in turn are faster than DRAM. Despite these differences in architecture and performance, all of these types of memory have common features. In particular, they all contain memory cells that are each capable of storing a bit of data (i.e. a single "1" or a "0"). Furthermore, they all contain control circuitry that allows information to be read from or written to the memory cells.
30. The '148 patent also teaches using the microprocessor in a multiprocessor environment. An array of microprocessors as described in the '148 patent provides an extremely small but powerful computer. The microprocessors communicate with each other over interface ports that the '148 patent describes as being a serial input/output interface. The '148 patent teaches that these interface ports can include six lines, some of which are used to transfer data and others which are used to transfer control signals. While these interface ports can be used for communicating with other microprocessors, they can also be used for communication with other devices that are external to the microprocessor.
31. The '148 patent, like the '336 patent, teaches using a ring-oscillator to provide a system clock that is on the same chip as the microprocessor, and which is therefore subject to the same variations in operating conditions, such as temperature and voltage, or from variations in manufacturing. '584 Patent
32. The '584 patent relates to the manner in which operands or instructions to be accessed by a microprocessor can be located. Microprocessors operate by reading and executing a series of "instructions." An instruction is a command to a processor that tells the processor what operation to perform. Examples of operations are "add X to Y," "load data from memory location A," and so on. Instructions are usually represented to the processor as sequences of bits conforming to the processor's particular rules. The bit sequence usually includes a portion that specifies the action to be taken (such as "add" or "load" in the examples above) and another portion that specifies the data to be operated on (such as X, Y and A in the examples above).
The portion that specifies the action to be taken is generally referred to as an "opcode" and the portion that specifies the data as the "operand."
33. Instructions are stored in a memory device, usually in the order in which they are to be executed. The microprocessor includes circuits that fetch the instructions from the memory device into a special storage area called an "instruction register." Additional circuits translate the instructions in the instruction register into control signals that cause the microprocessor to execute the operation specified by the instruction. The process of generating these control signals is known as "decoding.";
34. Normally, instructions are fetched and executed in the order they are stored in memory. The processor has a register called a "program counter" that stores the address of a current instruction, and the counter is incremented to the address of the next instruction when it is time to fetch that instruction.
35. This normal sequential program "flow" can be redirected using a type of instruction called a "control flow" instruction. Control flow instructions change the value stored in the program counter so that the next instruction fetched is not necessarily the next instruction in memory. I refer to the alternative instruction selected by the control flow instruction as a "target instruction." The ability to redirect program flow is a valuable tool in programming.
36. In many processors, accessing memory to retrieve instructions is relatively slow compared to the speed at which the microprocessor can execute the operations. Consequently, it can be a challenge to keep the instruction register supplied with instructions so that the CPU doesn't have to wait to be told what to do next. The '584 patent relates to improvements in instructions and instruction processing that can help to keep the CPU supplied with instructions.
37. The improvements relate to techniques that can reduce the average size of the instructions, that is, the number of bits needed to tell the processor what to do. First, instead of fetching one instruction at a time into the instruction register, the processor disclosed in the '584 patent fetches an "instruction group"; that can include multiple instructions. Fetching multiple instructions at once means the processor can do more work before it needs another group of instructions, allowing the slower memory more time to retrieve the next group.
38. In the general case of a control flow instruction, the target instruction could be anywhere within an instruction group. The '584 patent teaches that target instructions are advantageously aligned at the beginning of an instruction group. As a result, when control flow is redirected, the processor always receives a full group of instructions that it can execute. This helps to keep the processor busy when the time between successive fetches is large.
39. Another technique taught in the '584 patent is reducing the number of bits required for a single instruction so that a group can include more instructions. One way to reduce the number of bits in the instruction is to rely on the existence of the instruction groups to assist the processor in finding operands that are to be accessed when executing a first instruction. For example, some instructions include operand data as part of the instruction. Operand data included in an instruction is referred to as an "immediate operand," and the immediate operand
needs to be extracted from the instruction register and delivered to the CPU. One aspect of the '584 patent relates to efficient techniques for placing immediate operands at certain positions within an instruction group to make them easier to locate. Level of Ordinary Skill in the Art of the MMP Patents-In-Suit
40. In my opinion, the MMP patents-in-suit were addressed to a person with at least a bachelor's degree in electrical engineering or computer science and having approximately three to five years of experience in the field of microprocessor design and programming. This person would readily understand the conceptual design of a microprocessor and its execution using programmed instructions. The person of ordinary skill would have had access to a library of technical publications, periodicals, and textbooks. I believe a person with this background would have the requisite knowledge that I described in the "Field of the MMP Patents-In-Suit"; section above.
DISPUTED TERMS
41. In this section, I analyze and give my justification and support for what I believe is a correct interpretation of the disputed terms and limitations of the MMP patents-in-suit. All exhibits to which I refer are attached to the Declaration of Roger L. Cook.
Disputed Terms: '336 Patent
Disputed Term: "Microprocessor"
Disputed Term
Claims Plaintiffs Defendants
microprocessor 1-10 an electronic circuit that executes programmed an electronic circuit that uses a central processing unit to instructions and is capable of interfacing with input/output circuitry and/or memory circuitry interpret and execute programmed instructions
42. I understand that TPL proposes that the term "microprocessor" be construed as "an electronic circuit that executes programmed instructions and is capable of interfacing with input/output circuitry and/or memory circuitry." I also understand that the defendants propose that this term be construed as "an electronic circuit that uses a central processing unit to interpret and execute programmed instructions." I believe that TPL's proposed construction is correct.
43. A person of ordinary skill in the art would understand that a microprocessor must be capable of interfacing with input/output circuitry and/or memory circuitry. In a typical computer, for example, a microprocessor reads instructions that are stored in memory, reads data that is stored in memory, and writes data into memory. Furthermore, a microprocessor communicates with peripheral devices such as hard drives, keyboards, and printers. Each of these peripheral devices includes its own input/output circuitry (i.e. different input/output circuitry than that which is present on the microprocessor itself). The input/output circuitry is necessary for that peripheral device to send data to and/or receive data from the microprocessor. If a microprocessor did not have the ability to interface with the input/output circuitry of peripheral devices or with memory circuitry, the microprocessor would not be able to perform any useful function. Therefore, I agree with TPL's proposed construction. Disputed Term: "An Entire Ring Oscillator Variable Speed System Clock in Said Integrated Circuit" Disputed Term Claims Plaintiffs defendants an entire ring oscillator variable speed system clock in said integrated circuit 1-2 a ring oscillator that generates the signal(s) used for timing the operation of the CPU, capable of operating at speeds that can change, where the ring oscillator is located entirely on the same semiconductor substrate as the CPU a ring oscillator variable speed system clock that is completely on-chip and does not rely on a control signal or an external crystal/clock generator
44. For brevity, I will refer to “an entire ring oscillator variable speed system clock in said integrated circuit” herein as "an entire ring oscillator."
45. I believe that Plaintiffs' proposed claim construction for this term is correct for several reasons. First, it explains that the ring oscillator is “located entirely on the same semiconductor substrate as the CPU,” which I believe is consistent with the specification and the prosecution history of the ‘336 patent. Specifically, the specification states: “Clock circuit 430 is the familiar ‘ring oscillator’ used to test process performance [i.e., the results of integrated circuit manufacturing processes]. The clock is fabricated on the same silicon chip as the rest of the microprocessor 50.” '336 Patent 16:56-58, Ex. 1 (parenthetical added) ("'336, 16:56-58"). Further, the specification notes that “[t]he ring oscillator 430 is useful as a system clock because its performance tracks the parameters which similarly affect all other transistors on the
same silicon die.” '336, 16:63-67. Also, the specification explains that “[s]ince the microprocessor 50 ring oscillator clock 430 is made from the same transistors on the same die as the latches and gates, it too will operate slower (oscillating at a lower frequency), providing compensation which allows the rest of the chip’s logic to operate properly.” '336, 17:5-10. Similar statements were made in the prosecution history. See Amd. 7/03/97 at 4-5, Ex. 8 and Amd. 2/06/98 at 3-4, Ex. 9. Thus, all of these passages demonstrate that the ring oscillator system clock is located entirely on the same semiconductor substrate as the CPU, which provides the benefit that the ring oscillator’s performance or speed will track those same performance parameters of the CPU as operating conditions vary, providing the advantages described in the ‘336 patent.
46. I also believe that Plaintiff’s construction is correct because the entire ring oscillator “generates the signal(s) used for timing the operation of the CPU.” The specification states this fact: “The microprocessor 50 uses the technique shown in Figs. 17-19 to generate the system clock and its required phases.” '336, 17:54-55 (emphasis added). Because Figures 17-19 describe the ring oscillator variable speed clock 430 and its operation, the '336 patent therefore teaches that the entire ring oscillator generates the signals used for timing the operation of the CPU. The specification confirms this when it notes one potential benefit of the invention that “y deriving system timing from the ring oscillator 430, CPU 70 will always execute at the maximum frequency possible, but never too fast.” '336, 16:67–17:2.
47. Further, I believe that the Plaintiffs’ construction is correct because the entire ring oscillator is “capable of operating at speeds that can change.” The changes in the "speed" of the ring oscillator, which in this context refers to its frequency, track the corresponding changes in the CPU because both devices are on the same semiconductor substrate, which is a key point of the invention of the ‘336 patent. The specification provides an example of the capability of the ring oscillator to operate at different speeds, depending on the ambient temperature: "The ring oscillator frequency is determined by the parameters of temperature, voltage, and process. At room temperature, the frequency will be in the neighborhood of 100 MHz. At 70 degrees Centigrade, the speed will be 50 MHz." '336, 16:59-63. (Room temperature is approximately 20 degrees Centigrade.) The specification also notes that the speed of the ring oscillator and the CPU may vary up to four-fold: “The CPU 70 executes at the fastest speed possible using the adaptive ring counter clock 430. Speed may vary by a factor of four depending upon temperature, voltage, and process.” '336, 19-22. Similar statements were made in the prosecution history. See Amd. 7/03/97 at 4-5, Ex. 8 and Amd. 2/06/98 at 3-4, Ex. 9. Thus, based on these passages, I believe that one of ordinary skill understands that the entire ring oscillator is “capable of operating at speeds that can change.”
48. In contrast to the Plaintiffs’ technically accurate construction for the “entire ring oscillator” limitation, which is consistent with the teachings of the ‘336 patent, the Defendants' proposed claim construction is unduly narrow and limiting, and is not supported by the patent or file history. It is a negative limitation in the sense that it carves out numerous exclusions or exemptions for "an entire ring oscillator" ("… does not rely on a control signal or an external crystal/clock generator"). One of ordinary skill might only find such a negative limitation useful if the resulting scope of the limitation is clear, but I believe that Defendants’ negative limitation does not provide sufficient guidance to such a person trying to determine whether he or she is practicing the invention. Instead, this construction would only inform of certain cases in which infringement may not occur. However, if a particular device or its use does not clearly meet one of the exemptions, a person of ordinary skill would be left without guidance as to whether that device or use practices this limitation. Defendants’ negative limitation is also problematic because it does not rule out other possible exclusions (a difficulty of multiple-exception negatives), nor does it define the universe of what is included affirmatively within the limitation. For this reason, a person of ordinary skill would not find this type of negative limitation technically useful.
49. Another reason Defendants' proposed construction is unduly narrow and limiting is that is purports to exclude all potential types and uses of an external crystal. For support, the Defendants may point to statements made by the applicants' attorney in the prosecution history with respect to crystals, which I have reviewed in my analysis. However, those statements were made in a very specific context, i.e., trying to overcome the examiner's rejection based on the Magar prior art reference. The Magar reference teaches the use of a traditional crystal oscillator in conjunction with a clock generator circuit to provide internal timing signals. The Magar crystal oscillator includes an off-chip crystal, connected between pins X1 and X2 of a clock generator, where the crystal controls the frequency of the CPU clock. In other words, while the clock generator circuit in Magar provides the timing signals for the CPU by modifying the output of the external crystal, the frequency or rate of those timing signals is determined by the fixed frequency of the crystal connected to the clock generator. Amd. 2/06/98 at 4, Ex. 9. According to the file history of the '336 patent, an external crystal in a traditional crystal oscillator is specifically utilized to provide a fixed-frequency clock: “The single, fixed, oscillation frequency of the crystal is determined by how the device is manufactured, i.e., how the crystal is cut and trimmed and other factors. Crystals are used precisely for this purpose; they oscillate at a given frequency within a tolerance determined by their manufacture.” Id. By using an external, fixedfrequency crystal not subject to the same variations in operating conditions and process parameters as the CPU, the crystal oscillator of Magar will not vary together with the CPU, and will not change with respect to these variations in temperature, voltage, or process parameters. Amd. 7/03/97 at 3-4, Ex. 8.
50. In contrast to the fixed frequency of the Magar crystal oscillator, the invention of the '336 patent is variable-speed, in that its frequency and operating characteristics (e.g., transistor propagation delay) change with variations in voltage and temperature on the semiconductor substrate, and with respect to process variations from when the chip was manufactured. Also, because the ring oscillator and the CPU are located on the same semiconductor substrate, the variations in voltage, temperature, and process parameters affect each of these circuit elements relatively equally, so the speed and operating characteristics of each will vary together. The "variable-speed" nature of the '336 patent invention's ring oscillator, and the "vary together" nature of the changes in the ring oscillator and CPU, are both achieved because the "entire" ring oscillator is on the same semiconductor substrate as the CPU. This fact was highlighted by applicants' attorney in distinguishing the '336 patent invention from the crystal oscillator of Magar, which uses an external crystal as a fixed-frequency oscillator that does not vary together with the speed of the CPU. Amd. 7/03/97 at 3-5, Ex. 8; Amd. 2/06/98 at 3-4, Ex. 9.
51. A traditional crystal oscillator, however, is not the only use of an external crystal in conjunction with a system clock. For example, a crystal can be used as the source of a reference signal, as opposed to the source of a clock signal itself. An example of a crystal used as a reference signal would be in a delay-locked loop (DLL). A DLL is used to account for delays in the distribution of a clock signal across a chip (such as by a clock tree), and uses variable-delay lines to adjust the delay of the clock signal for individual circuit elements on the
chip. More specifically, a DLL uses a set of controllable delay elements, each set corresponding to a different circuit element on a chip, to output a delayed reference signal (i.e., the internal clock signal), which is then compared to the actual reference signal (i.e., the external clock signal). The result of that comparison is used to generate a control signal for the controllable delay elements to compensate for the delay through that particular circuit element, in effect by providing offsetting delay, thereby delay-locking the internal clock signal with the external clock signal for that circuit element. Thus, the internal clock signal is not just the external clock signal generated from the external crystal, but rather that signal plus some offsetting delay determined and provided by the DLL mechanism. The key point is that there are other uses of an external crystal in conjunction with a system clock, like the DLL example, that are entirely different than the traditional crystal oscillator of Magar, and which were never even in front of the examiner. 52. Because the applicants’ attorney’s remarks in the file history were about a specific use of an external crystal – i.e., a traditional crystal oscillator – and had no relation to other uses of an external crystal, like a DLL, it is my opinion that Defendants’ construction is unduly narrow since it excludes all uses of an external crystal. Furthermore, this result illustrates why the use of a negative limitation is so problematic and contrary to the views of one of ordinary skill in the art, in that we are trying to define "an entire ring oscillator" by what it is not. Here, the exemption is too broad, which renders the entire limitation too narrow, in that it purports to exclude all external crystals. Thus, the proposed claim construction is unduly limiting and restrictive, and in effect reads limitations into the claims (by excluding all uses of an external crystal) that were never even discussed during the prosecution of the patent. Alternatively, if Defendants' construction excludes some types of external crystals but not others, then the definition is vague and ambiguous in that it does not provide enough guidance to one of skill in the art to understand what types of external crystals are excluded.
53. Not only is Defendants' proposed construction vague and ambiguous because it is unclear which uses of an external crystal are excluded, it is also similarly vague and ambiguous in excluding the use of any “control signal” and/or “external … clock generator.” The term “control signal” is so broad as to seemingly apply to any signal used to control a circuit, regardless of the purpose of the control, or the type of control technique used. Thus, the construction would exclude all forms of ring oscillators that receive control signals, for example voltage-controlled oscillators (VCOs) and current-controlled oscillators (ICOs), which utilize voltage or current, respectively, to change the frequency of the oscillation. However, these types of ring oscillators were not described in the example provided in the specification of the ‘336 patent, and certainly not in the context of being excluded from the invention, nor were they at issue in the prosecution history. Yet, Defendants’ construction suggests that a person of ordinary skill would summarily exclude them from the scope of the claims of the '336 patent. This is not a sensible view, and not one that a person of ordinary skill seeking to understand the scope of the claims would adopt after reviewing the patent and the file history. 54. As support for their construction's requirement that a "control signal" cannot be relied upon (again, note the awkwardness of a negative limitation), Defendants may identify the portion of the prosecution history where applicants' attorney made statements to overcome the Sheets prior art reference. (This is my speculation as I do not see any other basis that relates to this proposition in the claims, specification, or prosecution history.) Sheets teaches a digital voltage-controlled oscillator (VCO), where a digital word is provided to an off-chip VCO to set it's frequency. The applicants' attorney distinguished over Sheets by noting that "n Sheets, a command input is required to change the clock speed," and that, in the present invention, "no command input is necessary to change the clock speed." Amd. 1/08/97 at 4, Ex. 6. (Note that the applicants' attorney refers to "command input," not "control signal." The Defendants are trying to broaden the scope of the exclusion without any basis, as a "control signal" is broader than a "command input," to the extent that this term can be understood.) These statements by applicants' attorney concern how a "command input"; is used in Sheets to cause programmed changes to the clock frequency, in contrast to the automatic changes of the clock frequency in the ‘336 invention with respect to variations in temperature, voltage, process parameters, etc. In other words, the issues centered on the "variable-speed" and the "vary together" limitations, and not on what types of voltage-controlled oscillators qualify as "an entire ring oscillator." Amd.
7/03/97 at 5, Ex. 8. I believe that a person of ordinary skill in the art, focusing on this discussion in the prosecution history, would conclude that the statements made about Sheets concern whether variations in frequency in the oscillator are due to changes in operating parameters like voltage and temperature (i.e., automatic changes), or are due to "command inputs" like the digital word issued by the microprocessor to the VCO in Sheets (i.e., programmed changes). That same person of ordinary skill would not categorically rule out all VCOs that receive a “control signal.”
55. I also believe that one of ordinary skill in the art would be confused by the portion of Defendants' construction stating that an entire ring oscillator cannot rely on "an external crystal/clock generator," particularly because this definition does not find support in the specification or prosecution history. First, a crystal and a clock generator are not equivalent at all, so I do not understand the Defendants' suggestion of such equivalence by use of the slash (“/”) between the terms. Second, there is no substantive discussion in the specification or prosecution history of an external clock generator, only the on-chip clock generator of the Magar reference in the file history. Third, the applicants' attorney did not distinguish over Magar by arguing that the Magar reference teaches a discrete clock generator and the '336 patent does not require such a circuit, but rather that Magar does not teach an entire oscillator on the integrated circuit because the crystal portion of the oscillator circuit in Magar is off-chip, and therefore would not vary with temperature, voltage, etc., in the manner described in the '336 patent. Amd. 2/06/98 at 4-5, Ex. 9. In other words, the clock generator of Magar alone did not comprise the entire oscillator. Thus, one of ordinary skill would understand that the presence or absence of an on-chip clock generator was not the basis of distinguishing the ‘336 invention over Magar, and would not read such a limitation into the claims. 56. I have already described why a carte blanche exclusion of all external crystals is inappropriate and inconsistent with the file history of the ‘336 patent. Similarly, the “external clock generator” exclusion finds no support in the specification or file history. To support the portion of their construction stating that an entire ring oscillator does not rely on "an external crystal/clock generator," the Defendants may identify certain statements made in the prosecution history to distinguish over Magar. (Again, I am speculating, but I do not see any other basis that relates to this proposition in the claims, specification, or prosecution history.) It is illuminating to consider the actual statements that Defendants might rely on for this portion of their construction (with emphasis added to the most pertinent language): "The chip 10 includes a clock generator 17 which has two external pins X1 and X2 to which a crystal (or external generator) is connected.” Amd. 2/06/98 at 4, Ex. 9 (quoting Magar). As a self-contained on-chip circuit, Magar’s clock gen is distinguished from an oscillator in at least that it lacks the crystal or external generator that it requires. Id. The Magar teaching is well known in the art as a conventional crystal controlled oscillator. It is specifically distinguished from the instant case in that it is both fixed-frequency (being crystal based) and requires an external crystal or external frequency generator. Id. at 5.
57. One key point of these passages is that nowhere do they discuss an external clock generator. Rather, these passages describe an “external generator” or an “external frequency generator.” An “external generator” or “external frequency generator” has nothing to do with an external clock generator. Instead, an external frequency generator is simply an off-chip oscillator, an example of which is a crystal oscillator. In contrast, a clock generator is a means to modify the output of an oscillator, e.g., “to produce additional required clock signals for the system.” Amd. 7/03/97 at 4, Ex. 8. Since the clock generator modifies the output of the oscillator, they cannot literally be the same device. Thus, because Magar’s teachings and the applicants’ attorneys statements were only about an “external frequency generator” (i.e., oscillator) and not an “external clock generator,” this portion of Defendants’ definition is not supported by the file history. Rather, any reliance on these statements as purported support for Defendants’ definition would be incorrect and a misreading of the prosecution history, as well as inconsistent with how one of ordinary skill would view the scope of the claims of the ‘336 patent based on the file history.
58. For these reasons, I believe that a person of ordinary skill in the art would understand that "an entire ring oscillator variable speed system clock in said integrated circuit" is "a ring oscillator that generates the signal(s) used for timing the operation of the CPU, capable of operating at speeds that can change, where the ring oscillator is located entirely on the same semiconductor substrate as the CPU." Therefore, I believe that Plaintiffs' construction for this term is the correct one.
Disputed Term: "An Entire Ring Oscillator System Clock Constructed of Electronic Devices Within The Integrated Circuit" Disputed Term Claims Plaintiffs Defendants an entire ring oscillator system clock constructed of electronic devices within the integrated circuit 3-5 a ring oscillator that generates the signal(s) used for timing the operation of
the CPU, where the ring oscillator is located entirely on the same semiconductor a ring oscillator system clock that is completely on-chip and does not rely on a control signal or an external crystal/clock generator substrate as the microprocessor
59. For the same reasons I discussed in conjunction with the "entire ring oscillator" limitation above (i.e., for claims 1-2), I believe that a person of ordinary skill in the art would understand that "an entire ring oscillator system clock constructed of electronic devices within the integrated circuit" is "a ring oscillator that generates the signal(s) used for timing the operation of the CPU, where the ring oscillator is located entirely on the same semiconductor substrate as the microprocessor."; The main differences between the present limitation and the corresponding limitation discussed above are the absence of the “variable-speed” language, and the addition of the phrase “constructed of electronic devices within the integrated circuit,” but they are otherwise the same. Therefore, my reasoning discussed above applies equally to this limitation. As for the “constructed of electronic devices within the integrated circuit” language, I view this as being functionally equivalent to the “in said integrated circuit” language of the
corresponding limitation above, and base my present opinion on that reasoning as well. Therefore, for these reasons, I believe that Plaintiffs' construction for this term is the correct one. Disputed Term: "An Entire Oscillator Disposed Upon Said Integrated Circuit Substrate and Connected to Said Central Processing Unit, Said Oscillator Clocking" Disputed Term Claims Plaintiffs Defendants an entire oscillator disposed upon said integrated circuit substrate and connected to said central processing unit, said oscillator clocking 6-9 an oscillator that generates the signal(s) used for timing the operation of the CPU,
where the oscillator is located entirely on the same semiconductor substrate as the CPU and is electrically coupled to the CPU an oscillator that is completely on-chip and does not rely on a control signal or an external crystal/clock generator
60. For the same reasons I discussed in conjunction with the "entire ring oscillator" limitation above (i.e., for claims 1-2), I believe that a person of ordinary skill in the art would understand that "an entire oscillator disposed upon said integrated circuit substrate and connected to said central processing unit, said oscillator clocking" is "an oscillator that generates the signal(s) used for timing the operation of the CPU, where the oscillator is located entirely on the same semiconductor substrate as the CPU and is electrically coupled to the CPU." The main differences between the present limitation and the corresponding limitation discussed above is the change from “ring oscillator” to “oscillator,” the absence of the “variable-speed” language (which still applies based on the larger context of the claim), and the addition of the “connected to said central processing unit” and “said oscillator clocking” language.
61. The only difference between the claim limitations that potentially affects my analysis is the reference in the present limitation to “oscillator” instead of “ring oscillator." A ring oscillator is a form of an oscillator, but there are other types of oscillators as well. Therefore, the “oscillator” limitation is broader than the “ring oscillator” limitation. However, the basis for distinguishing over Sheets and Magar in the file history applies equally whether considering the claims of the ‘336 patent directed to an “oscillator,” or those directed to a “ring oscillator.” In other words, it was not the specific type of oscillator ─ a ring oscillator ─ that was the basis for distinction, but rather the “entire” oscillator being on-chip (Magar), or the changes in frequency of the oscillator occurring automatically in response to changes in voltage, temperature, etc. (Sheets). In fact, the whole discussion about Magar was in the context of “oscillator,” not “ring oscillator.” See Amds. 7/03/97 and 2/06/98, Exs. 8-9. Thus, my discussion of the statements made in the file history are equally applicable to the present “oscillator” limitation. Also, since Defendants use the same unhelpful negative limitations in the present limitation as for the “entire ring oscillator” limitation, my reasoning as to why that definition is incorrect would apply here as well.
62. I believe that Plaintiffs' construction is also correct because the reference to “said oscillator clocking” is actually, in full, “said oscillator clocking said central processing unit at a clock rate.” I understand this limitation to be functionally equivalent to the “system clock” limitations of claims 1-5, and therefore the same reasoning I used for that limitation would apply to the present limitation. I also believe that the “connected to said central processing language” means “electrically coupled to the CPU,” since it is the electrical coupling that provides an electrical path for the signals used for timing the operation of the CPU, as generated by the oscillator, to the CPU itself.
63. Therefore, for these reasons, I believe that Plaintiffs' construction for this term is the correct one. Disputed Term: "An Entire Variable Speed Clock Disposed Upon Said Integrated Circuit" Disputed Term Claims Plaintiffs Defendants an entire variable speed clock disposed upon said integrated circuit 10 a circuit that generates the signal(s) used for timing the operation of the CPU, capable of operating at speeds that can change, where the circuit is located entirely on the same semiconductor substrate as the CPU a variable speed clock that is completely on-chip and does not rely on a control signal or an external crystal/clock generator
64. For the same reasons I discussed in conjunction with the "entire ring oscillator" limitation above (i.e., for claims 1-2), I believe that a person of ordinary skill in the art would understand that “an entire variable speed clock disposed upon said integrated circuit” is "a circuit that generates the signal(s) used for timing the operation of the CPU, capable of operating at speeds that can change, where the circuit is located entirely on the same semiconductor substrate as the CPU." The main differences between the present limitation and the corresponding limitation discussed above are the change from “entire ring oscillator variable speed system clock” to “entire variable speed clock,” and the absence of the “system clock” language. Here, the reference to “an entire variable speed clock” indicates that the entire circuit required to
generate the signal(s) used for timing the operation of the CPU is on-chip and subject to the same variations in operating parameters (e.g., voltage or temperature) as the CPU, resulting in the automatic changes in frequency described above. For the “variable speed clock” portion of the limitation, my analysis remains the same as for the “system clock” limitations above because I believe that, in context, one of ordinary skill in the art would understand “variable speed clock” here to be the same as “system clock” in the other claims. And finally, my reasoning as to why Defendants’ negative definition (which they also use for the present limitation) would not be adopted by one of ordinary skill in the art applies equally here. Thus, for all these reasons, I believe that Plaintiffs’ construction for this term is the correct one. Disputed Terms: "Varying Together / Vary Together / Varying … in the Same Way / Varying in the Same Way" Disputed Term Claims Plaintiffs Defendants varying together vary together varying . . . in the same way 1-2 both increase or both decrease increasing and decreasing by the same amount
65. These different terms, as they appear in the claims of the ‘336 patent, are used in the same manner but with slightly different phrasing among the claims. However, I believe that each phrase is meant to define the same principle, applicable to each claim's specific context, and that a person of ordinary skill in the art would rely on a single definition for each of these related phrases. The Defendants’ definition also supports this concept, since it also uses a single definition for all four phrases. For brevity, I will refer to these four phrases collectively as the “varying together” limitations. While the meaning of the “varying together” limitations is the same among the claims, I note that the different claims specify slightly different elements that actually do the varying together. For example, claim 1 specifies that the “processing frequency capability of said central processing unit” and “a speed of said ring oscillator variable speed system clock” vary together. In claim 3, it is the "operating characteristics of electronic devices" of the entire ring oscillator and of the microprocessor that vary together. 66. I believe that the Plaintiffs’ definition for the “varying together” limitations – that the items being compared both increase or both decrease – is supported by the specification and the prosecution history of the ‘336 patent, and is therefore the correct interpretation. The ‘336 patent notes that transistors have propagation delays, which is the amount of time it takes before the output of a transistor becomes valid after being provided with an input, sometimes referred to as the “switching speed” of the transistor. The propagation delays of transistors are affected by
operating conditions, like voltage and temperature, and variations in manufacturing parameters. See '336, 16:44-53. In the context of the invention of the ‘336 patent, this has at least two effects. First, the speed of the ring oscillator (or oscillator in claims 6-9, or variable-speed clock in claim 10) will change based on variations in these parameters. For example, as the temperature of the ring oscillator goes up, the switching speeds of its transistors goes down, and hence its operating speed goes down. As mentioned previously, the ‘336 patent provides an example of this correspondence: “The ring oscillator frequency is determined by the parameters of temperature, voltage, and process. At room temperature, the frequency will be in the neighborhood of 100 MHz. At 70 degrees Centigrade, the speed will be 50 MHz.” '336, 16:59- 63. Of course, as the speed of the ring oscillator varies, so too will the speed of the CPU, as the ring oscillator generate(s) the signals used for timing the operation of the CPU. 67. A second effect of the variations in temperature, voltage, and process parameters is the range of speeds at which the CPU can operate. In the example given in the specification, this is described in the context of the “maximum theoretical performance.” '336, 16:50-53. The specification teaches that the maximum theoretical performance, or the maximum frequency a CPU can operate at and still provide a valid output, will change with variations in temperature, voltage, and process parameters. This is because the maximum theoretical performance is set in part by the transistor propagation delays of the transistors that make up the CPU, as the speed of the CPU cannot exceed these propagation delays without potentially causing errors. Actually, it is a bit more complicated than this, because there are different logic paths within the CPU, and the maximum theoretical performance is actually determined largely by the delays in propagating a signal through the slowest logical path, which is dependent on the switching speed of the transistors in that particular path as well as their actual configuration. For purposes of this discussion, however, it is convenient just to focus on the relationship between the propagation delays of the transistors in the CPU and the range of speeds over which the CPU can operate
(i.e., without producing errors). When the temperature of the CPU goes up, its maximum theoretical performance goes down.
68. The '336 patent specification describes how the ring oscillator and the speed of the CPU (or the range of speeds that the CPU can operate at) vary together: The ring oscillator 430 is useful as a system clock . . . because its performance tracks the parameters which similarly affect all other transistors on the same silicon die. By deriving system timing from the ring oscillator 430, CPU 70 will always execute at the maximum frequency, but never too fast. For example, if the processing of a particular die is not good resulting in slow transistors, the latches and gates on the microprocessor 50 will operate slower than normal. Since the microprocessor 50 ring oscillator system clock 430 is made from the same transistors on the same die as the latches and gates, it too will operate slower (oscillating at a lower frequency), providing compensation which allows the rest of the chip's logic to operate properly. '336, 16:63-17:10. Thus, the specification describes an example of “varying together” in which the switching speed of the transistors of the CPU slows down, and hence the range of speeds over which the CPU can operate decreases, but this is offset by the fact that the ring oscillator, being formed from transistors on the same semiconductor substrate as the CPU, simultaneously slows down as well. This ensures that the output of the CPU remains valid. In another embodiment, “[t]he CPU 70 executes at the fastest speed possible using the adaptive ring counter clock 430. Speed may vary by a factor of four depending upon temperature, voltage, and process.” '336, 17:19-22.
69. The file history also explains that the varying together occurs "similarly"; and "automatically" (emphasis added): That is, the operational speed of the microprocessor and ring oscillator clock are designed to vary similarly as a function of variation in temperature, processing and other parameters affecting circuit performance. Amd. 4/11/96 at 7, Ex. 4. Crucial to the present invention is that since both the oscillator or variable speed clock and driven device are on the same substrate, when the fabrication and environment parameters vary, the oscillation or clock frequency and the frequency capability of the driven device will automatically vary together. Amd. 7/03/97 at 5, Ex. 8.
70. Importantly, what the specification does not teach is that there is an exact 1:1 correspondence in the amount of the change of the transistor propagation delays and/or speed of the ring oscillator, and of the change in the transistor propagation delays and/or speed of the CPU. For one thing, as mentioned above, the maximum theoretical performance of the CPU is not only a function of the switching speed of its transistors, but also of its logical pathways and how the transistors in those pathways are configured. Thus, just because the switching speeds of transistors across the substrate decreases (for example), this does not mean that all circuit elements are affected equally. What is critical is that the direction of the change (i.e., increasing or decreasing) of the performance parameters of both the ring oscillator and the CPU change in the same direction. Thus, if the speed of the CPU slows down, so too must the speed of the ring oscillator. In other words, a person of ordinary skill in the art would understand the “vary together” limitations to be referring to a qualitative correspondence – i.e., that both values increase or decrease – and not a quantitative (such as 1:1) correspondence. 71. I believe that Defendants’ definition for the “varying together” terms, which requires a 1:1 correspondence (“increasing and decreasing by the same amount”) is unduly narrow and limiting, and seeks to inject a limitation into the claims that is not found in the ‘336 patent specification or file history. I cannot find one reference in the specification or file history to a change in speed or propagation delays that is exactly matched between the ring oscillator and the CPU. Further, one of ordinary skill in the art would understand there are reasons why this limitation in practice would not be necessary or even feasible in a real-world device. First, while the variations in temperature, voltage, and processing parameters will apply generally to the same semiconductor substrate, one of ordinary skill would expect that there may be microvariations in those parameters across different parts of the substrate. This of course would have different impacts on the amount of change of the propagation delays across the (microscopic) transistors. In a real-world context, one of ordinary skill would never expect to obtain exactly matched transistor propagation delays across an entire substrate, although the switching speeds would "vary together" as identified in Plaintiffs' definition. 72. The second reason that one of ordinary skill would not understand Defendants’ 1:1 correspondence to be required by the '336 patent is that the relationship between maximum theoretical performance of the CPU and the speed of the ring oscillator is not a set ratio, but rather a range of ratios. In other words, for the output of the CPU to remain valid, it is only important that the speed of the ring oscillator not exceed the maximum theoretical performance of the CPU, as limited by, in part, the propagation delays of the transistors of the CPU. So, it is perfectly acceptable that if the maximum theoretical performance of the CPU slows down due to an increase in operating temperature, the speed of the ring oscillator slows down even more, as this will not lead to errors. By corollary, if the temperature of the chip decreases, and hence the maximum theoretical performance of the CPU increases, it is not problematic if the speed of the ring oscillator increases by an amount less than the CPU. (There is also a minimum speed that the CPU must operate at to provide a valid output, but it is far removed from the maximum theoretical performance limit of the CPU and would not be an issue in the context of the variations in temperature, voltage, and process parameters described in the ‘336 patent.)
73. Thus, because there is not a technical requirement of 1:1 correspondence in the changes in the CPU versus in the ring oscillator, and because the patent specification and file history do not teach such a correspondence, a person of ordinary skill in the art would not consider Defendants’ definition a valid requirement of the claims of the ‘336 patent.
74. For these reasons, I believe that a person of ordinary skill in the art would understand that the "varying together" limitations mean "both increase or both decrease." Therefore, I believe that Plaintiffs' construction for this term is the correct one.Disputed Term: "Second Clock"; Disputed Term Claims Plaintiffs Defendants second clock 1-5 a clock not derived from the first clock No construction necessary,
but if construed: another clock
75. I understand the term "first clock"; in Plaintiffs' proposed construction as referring to the clock signal output of either the "ring oscillator variable speed system clock"; circuit (in claims 1 and 2) or the "ring oscillator system clock"; circuit (in claims 3-5). For conciseness, I will use "first clock signal" in this manner. 76. I also believe that "second clock"; refers to a clock signal, rather than to a clock circuit. Claim 1 refers to "a second clock independent of said ring oscillator variable speed system clock," and claim 3 refers to "a second clock independent of the ring oscillator system clock." Describing one clock circuit as "independent of" another clock circuit would likely be ambiguous to one of skill in the art, but describing one clock signal as "independent of" another clock signal "would be clear.
77. I believe that Plaintiffs' proposed claim construction is correct because it reflects the specification and file history, which indicate that the second clock signal is not derived from the first clock signal. Specifically, an embodiment of a microprocessor with a second clock signal is described in the '336 patent at 17:11-37 and shown in Fig. 17. In this example, the CPU 70 is clocked at a variable speed by the "adaptive ring counter clock 430" (id. at 17:20-21), which would provide a first clock signal, and the I/O interface 432 is clocked by "a conventional crystal clock 434" (id. at 17:25-27), which would provide a second clock signal. The crystal clock circuit 434 includes its own oscillator, and the clock signal produced by the crystal clock circuit 434 is derived from that oscillator, not from the ring oscillator that is the source of the first clock signal. Thus, in the only embodiment disclosed, it is apparent to me that the second clock signal is not derived from the first clock signal.
78. Furthermore, the specification states that the purpose of using two clocks is "decoupling the variable speed of the CPU 70 from the fixed speed of the I/O interface 432." Id. at 17:32-33. Such decoupling can be achieved only if the second clock is not derived from the first clock. In addition, the specification discloses that "[r]ecoupling between the CPU 70 and the interface 432 is accomplished with handshake signals on lines 436." Id. at 17:35-36. Handshake signals are well known in the art for coupling asynchronous devices or systems. If the clocks were synchronous, as would be the case if the second clock were to be derived from the first clock, then handshake signals would be unnecessary. Since standard practice in the art is not to use unnecessary signals, I believe that the use of handshake signals indicates that the second clock in the embodiment shown is not derived from the first clock.
79. The file history is also consistent with this view. In Amendment B, Applicants distinguished claims with limitations related to the "second clock"; from Schaire, U.S. Patent No. 4,453,229. Amd. 4/11/96 at 9, Ex. 4. Applicants observed that "Schaire provides no indication that bus interface 10 is clocked by a signal from a clock different from that used to clock the host microprocessor. That is, the origin of high-speed clock signal 230 (FIG. 1) provided to bus interface unit 10 does not appear to be described. Hence, Schaire fails to teach the claimed provision of separate, independent clock signals to an input/output interface buffer and a microprocessor."; Id. This example shows that Applicants regarded the use of a second clock signal not derived from the first clock signal as an important feature, and Plaintiffs' definition reflects this.
80. I believe that Defendants' proposed claim construction is not correct because their use of "another clock"; is overly broad. For example, in some contexts, a buffered or delayed version of a first clock signal could be identified by a person having ordinary skill in the art as "another clock signal." However, such a clock signal would not accomplish the decoupling that is described in the specification as the purpose of clocking the I/O interface using a second clock
81. For these reasons, I believe that a person of ordinary skill in the art would understand that a second clock is "a clock not derived from the first clock." Therefore, I believe that Plaintiffs' construction for this term is the correct one. Disputed Term: "External Clock"; Disputed Term Claims Plaintiffs Defendants external clock 6-10 a clock not derived from the first clock, and which is not originated on the same semiconductor substrate upon which the entire oscillator [claims 6-9] or the entire variable speed clock [claim 10] is located No construction necessary, but if construed: a clock not on the integrated circuit substrate
82. As with "second clock," discussed above, I understand the term "first clock"; in Plaintiffs' proposed construction as referring to the clock signal output of either the "oscillator" circuit (in claims 6-9) or the "variable speed clock"; circuit (in claim 10). For conciseness, I will use "first clock signal" in this manner.
83. It is also my understanding that "external clock"; refers to a clock signal, rather than to a clock circuit. Claim 6 refers to "an external clock, independent of said oscillator," and claim 10 refers to "an external clock wherein said external clock is operative at a frequency independent of a clock frequency of said [variable speed clock]." Describing one clock circuit as "independent of" another clock circuit would likely be ambiguous to one of skill in the art, but describing one clock signal as "independent of" another clock signal "would be clear.
84. I believe that Plaintiffs' proposed claim construction is correct because it reflects the specification and file history, which indicate that the external clock signal is not derived from the first clock signal and that "external" refers to a clock that does not originate on the substrate on which the entire oscillator or entire clock is located.
85. In the specification, an embodiment of a microprocessor with an on-chip oscillator and an external clock signal is described in the '336 patent at 17:11-37 and shown in Fig. 17. This is the same embodiment discussed above with regard to the meaning of "second clock"; in claims 1-5. As discussed above, the example shows that the second clock is not derived from the first clock. In addition, Fig. 1 shows a microprocessor chip with a pin (64) labeled "CLOCK-IN."; A person skilled in the art would understand that this pin is used to deliver to components on the chip a clock signal that originates externally to the chip. Since these are the only examples of an "external clock"; in the specification, the requirement of being "not derived from" the first clock applies to the external clock for all of the reasons I have stated above with respect to the "second clock."
86. Likewise, the statements from the file history regarding Schaire discussed above with reference to the "second clock"; in claims 1-5 apply equally to the "external clock." These statements reinforce my view that the construction of external clock should indicate that this clock is "not derived from the first clock," as Plaintiffs propose.
87. In addition to the reasons discussed above with reference to a "second clock," I believe that Plaintiffs' construction of "external clock"; is superior to Defendants' construction because Plaintiffs' construction better captures the distinction in scope between "external clock"; and "second clock," namely that the external clock originates somewhere other than on the substrate that contains the ring oscillator.
88. This construction is consistent with the example in the '336 specification (17:11- 37). The external clock in this example originates from the conventional crystal clock circuit 432 shown in Fig. 17, which is off the integrated circuit substrate that contains the ring oscillator system clock circuit 430.
89. It appears that Defendants agree that an "external clock"; must at least originate outside the integrated circuit substrate that contains the oscillator or variable speed clock, as Defendants' proposed construction includes "not on the integrated circuit substrate." 90. I believe, however, that Plaintiffs' construction is superior in clearly formulating the distinction between "second clock"; and "external clock." Defendants' construction is unclear as to the respect in which the external clock is "not on the integrated circuit substrate."
91. It is clear that the external clock signal must at some point be on the integrated circuit substrate because claims 6-10 specify a connection between the "external clock"; and an "on-chip input/output interface." Specifically, claim 6 recites that the external clock is "connected to said input/output interface." Similarly, claim 10 recites a step of "clocking said input/output interface" using the external clock. If the external clock signal is "not on the integrated circuit substrate" at any point, it cannot be connected to or used to clock an interface that is on the substrate. Thus, there must be some point at which the external clock signal is on the integrated circuit substrate.
92. I believe that Defendants' construction fails to specify any particular point at which the external clock signal is required to be "not on the integrated circuit substrate." Since Defendants' construction also fails to state that the external clock signal is not derived from the first clock signal, it is possible that a clock signal that is originated on the substrate, then sent off the substrate and subsequently returned to the substrate would be regarded as an external clock under Defendants' proposed construction. Plaintiffs' construction removes this possibility.
93. For these reasons, I believe that a person of ordinary skill in the art would understand that an external clock is "a clock not derived from the first clock, and which is not originated on the same semiconductor substrate upon which the entire oscillator (claims 6-9) or entire variable speed clock (claim 10) is located." Therefore, I believe that Plaintiffs' construction for this term is the correct one. Disputed Terms: '148 Patent Disputed Term: "Processing Unit" Disputed Term Claims Plaintiffs Defendants processing unit 4,7,8,10 an electronic circuit that controls the interpretation and execution of programmed instructions None given
94. I understand that TPL's proposed construction of the phrase "processing unit" in the '148 Patent is the same as its proposed construction of "central processing unit" in the '336 Patent. A person of ordinary skill in the art would understand that, in the context of the '336 and '148 Patents, these phrases would have the same meaning. In my opinion, both of these phrases should be construed consistently with TPL's proposed construction. Disputed Terms: "Memory/A Memory" Disputed Term Claims Plaintiffs Defendants memory, a memory 4,7,8,10 all of the storage elements on the substrate and the control circuitry configured to access the storage elements term is indefinite, but if construction is possible, an information storing array that does not include registers, cache or column latches
95. I understand that TPL proposes that the terms "memory" and "a memory" should be construed as "all of the storage elements on the substrate and the control circuitry configured to access the storage elements." I believe that this construction is consistent with the understanding of a person of ordinary skill in the art. Memory is generally understood to include storage elements such as capacitors in the case of DRAM, or floating gates in the case of flash memory, that can each store a single bit of data (i.e. a “1” or a “0”). Memory also includes control circuitry that is used to write data to the storage elements, read data from the storage elements, and refresh data stored in the storage elements. One of ordinary skill in the art would consider memory to include both the storage elements and the control circuitry. TPL's construction correctly includes both the storage elements and the control circuitry.
96. I understand that the defendants propose that the term "a memory" should be construed as "an information storing array that does not include registers, cache or column latches." I disagree with the defendants proposed construction because it excludes circuitry that one of ordinary skill in the art would consider to fall within the meaning of memory. Memory is generally understood to include all electronic circuitry that has the property of being capable of maintaining its state for some period of time. Registers, cache and column latches all have this property. Therefore, the defendants proposed construction is consistent with the understanding of a person of ordinary skill in the art.
97. One of ordinary skill in the art would consider registers to be memory. Registers are very fast memory that provide quick access to store various data, addresses or instructions used by a processor. Registers are typically classified by how many bits they hold, such as a 32-bit register or a 64-bit register. Registers can be implemented in a variety of ways, but often they are implemented as a register file, which is an array of registers typically consisting of static random access memory (SRAM) cells. Regardless of how they are implemented, registers have memory cells that are capable of maintaining their state for a period of time, and they include control circuitry, and therefore they are a type of memory.
98. One of ordinary skill in the art would consider cache to be memory. Cache is a broad term that generally applies to a block of memory that temporarily stores a duplicate of information that is stored elsewhere in a computer system, such as in main memory. The purpose of providing cache memory is to allow very fact access to information that is likely to be used by the processor. Like registers, cache memory on a processor often is implemented as SRAM. Therefore, like registers, cache memory has memory cells that are capable of maintaining their state for a period of time, and they include control circuitry, and therefore it is a type of memory.
99. One of ordinary skill in the art would also consider column latches to be memory. Column latches are storage devices typically used to store the portion of an address that corresponds to a particular column within an array of storage elements. For example, DRAM typically includes a two-dimensional array of storage elements, each storage element being capable of storing one bit of data. These storage elements can be thought of as being arranged as bytes, where each byte includes eight bits. Each byte (i.e. series of eight bits) may represent some kind of information, such as a number or a letter. If a processor wants to access a particular byte from DRAM, it must know which row and column within the DRAM where the byte is located. The location of the byte is called its address, which itself is a series of bits having a row component and a column component. To access the byte, the processor sends the address to the DRAM, which splits the address into its row component and its column component. The bits that represent the row address are generally stored in a row latch (i.e. storage element), and the bits that represent the column are generally stored in a column latch.
100. Column latches, like other latches, typically are made up of electronic circuits called flip-flops. A flip-flop can, in turn, be constructed in a variety of ways, but each of those ways involves some arrangement of transistors (which are simply electronic switches). Each flip-flop can store a single bit of data, and a series of flip-flops make up the column latches. The '148 Patent teaches using column latches in several innovative ways, such as using a 1024-bit column latch as a long video shift register to drive a CRT display directly, and using two 1024- bit column latches to operate as the equivalent of two 32x32-bit register arrays (with the advantage of the column latch being about twice as fast as a register array). Regardless of how they are used, column latches, like registers and cache memory, have memory cells that are capable of maintaining their state for a period of time, and they include control circuitry, and therefore they are a type of memory. Disputed Terms: "Total Area of Said Single Substrate/Total Area of Said Substrate/Area of Said Single Substrate/Area of Said Substrate/Area of Said Integrated Circuit Substrate" Disputed Term Claims Plaintiffs Defendants total area of said single substrate total area of said 4,7,8,10 the total surface of the supporting material upon or
within which is formed an interconnected array of area enclosed by the outermost edges of the substrate area of said single substrate area of said substrate area of said integrated circuit substrate circuit elements the surface of the supporting material upon or within which is formed an interconnected array of circuit elements
101. I understand that TPL proposes that these phrases should be construed as "the total surface of the supporting material upon or within which is formed an interconnected array of circuit elements" and "the surface of the supporting material upon or within which is formed an interconnected array of circuit elements." I believe that these constructions are correct and consistent with the understanding of a person of ordinary skill in the art.
102. A person of ordinary skill in the art would understand that a substrate has six surfaces, like a cube. Typically the top surface of the substrate includes active circuitry, but the side and bottom surfaces do not. A person of ordinary skill in the art would understand that when the '148 Patent refers to the area of the substrate, it is referring to only the portion of the substrate that includes active circuitry. When a person of ordinary skill in the art refers to the area of the substrate, he or she is concerned only with the portion of the substrate surface that includes active circuitry. This is for several reasons:
1) the regions with no active circuitry do not consume any power
2) the regions with no active circuitry do not cause interference
3) the regions with no active circuitry leave room for other components
103. A person of ordinary skill in the art is not concerned with portions of the substrate that do not consume power or cause interference. Similarly, a person of ordinary skill in the art is not concerned with areas that could be used for other components -- that is, until other components are actually placed there.
104. Furthermore, the discussion in the '148 Patent makes clear that the inventors were referring to only the active area of the substrate. The embodiment which includes a microprocessor incorporated on a DRAM is shown in Figure 9. In this figure, the memory clearly occupies a majority of the surface of the substrate containing active circuitry. If the area of the substrate were interpreted to also include the sides and the bottom surface of the substrate, then the memory in the device shown in Figure 9 would not occupy a majority of the surface of the substrate. A person of ordinary skill in the art, reading the '148 Patent, would understand that the inventors used these phrases to refer only to the areas containing active circuitry. Disputed Term: "Integrated Circuit Substrate" Disputed Term Claims Plaintiffs Defendants integrated circuit substrate 4,7,8,10 the supporting material upon or within which is formed an interconnected array of circuit elements a single supporting material upon or within which is formed a miniature circuit
105. I understand that TPL proposes that the phrase "integrated circuit substrate" should be construed as "the supporting material upon or within which is formed an interconnected array of circuit elements." I also understand that the defendants propose that this phrase be construed as "a single supporting material upon or within which is formed a miniature circuit." I agree with TPL's proposed construction.
106. The difference between TPL's and the defendants proposed constructions is that the former refers to an "interconnected array of circuit elements" whereas the latter refers to a "miniature circuit." I believe that TPL's proposed construction is consistent with the understanding of a person of ordinary skill in the art. The circuit elements could be digital components such as transistors, or analog components such as resistors and capacitors, or a combination of both. Regardless of which particular components make are used, they are
arranged in an interconnected array.
107. The defendants' proposed construction, however, is ambiguous in that it introduces the concept of size. It is unclear what the word "miniature"; in the defendants' proposed construction means -- that is, it is unclear what the circuit is being compared with. The world of electronic devices involves very small components relative to the types of devices humans typically interact with. In a sense, every electronic circuit can be considered "miniature." It is not clear, however, how the defendants are using this term. Therefore, I disagree with the defendants' proposed construction. Disputed Term: "Interface Ports for Interprocessor Communication" Disputed Term Claims Plaintiffs Defendants interface ports for interprocessor communication 8,10 channels through which data can be transferred between two separate processing units channels through which data is transferred between two separate processing units
108. I understand that TPL proposes that this phrase should be construed as "channels through which data can be transferred between two separate processing units." I also understand that the only difference between TPL's and the defendants' proposed constructions is that the defendants require that data be transferred between two separate processing units through the channels. I believe that TPL's proposed construction, and not the defendants' proposed construction, is correct.
109. The microprocessor disclosed in the '148 Patent includes 32 data lines, as well as several control lines, power and ground. These lines are shows in Figure 1 of the patent. The '148 Patent also teaches that 6 lines can be used for serial input/output with another processor. The '148 Patent does not, however, indicate which of the lines shown in Figure 1 are specifically used for multiprocessor communication. Rather, the '148 Patent teaches that the design of the microprocessor is flexible, and that some of the lines shown in Figure 1 can be configured to perform serial input/output with another processor. Those same lines, however, can be configured to perform some other input/output function.
110. A technique called memory-mapped input/output, in which different devices outside of the microprocessor are given different addresses, can be used to identify what type of device the interface port will communicate. If the address corresponds to another processor, then the interface port will be used for interprocessor communication. If the address corresponds to some other device, such as a printer, then the interface port will be used for communication with that device. The flexibility afforded by the design of the microprocessor disclosed in the '148 Patent is one of the key features that make if valuable. Therefore, a person of ordinary skill in the art would understand that while certain interface ports can be used for interprocessor communication, they do not have to be so used.
Disputed Terms: '584 Patent
Disputed Term: "Instruction Groups"
Disputed Term Claims Plaintiffs Defendants instruction groups 29 Sets of from 1 to a maximum number of sequential instructions, each set being provided to the instruction register as a unit and having a boundary. Sets of from 1 to a maximum number of sequential instructions, in which the execution of the instructions depends on each set being provided to the instruction register as a unit and in which any operand that is present must be right justified and which cannot encompass a single 32-bit RISC instruction.
111. I believe that Plaintiffs' proposed construction is consistent with the specification and file history of the '584 patent. The specification describes an embodiment in which the microprocessor "fetches instructions in 4-byte instruction groups. An instruction group may contain from one to four instructions." '584 Patent 19:17-18, Ex. 3 ("'584, 19:17-18"). The instructions are fetched into a 32-bit instruction register that holds the entire instruction group. See '584, 14:4-6 (Fig. 16). As is well known, a byte is 8 bits, and thus the 32-bit register is precisely the size needed to store a 4-byte (or 32-bit) instruction group. I understand that the sizes are used by way of example and do not believe that the term "instruction groups" should be limited to any specific size.
112. Instruction groups are used to hide memory latency, that is, the time required to fetch further instructions from memory. As explained in the specification, once an instruction group is fetched into the instruction register, the microprocessor determines whether any of the instructions will require access to memory. If not, then "the microprocessor initiates the memory fetch of the next sequential 4-byte instruction group"; so that "[w]hen the last instruction in the [current] group finishes executing, the next 4-byte instruction group is ready and waiting on the data bus needing only to be latched into the instruction register." Id. at 19:22-32.
113. Instruction groups also have well-defined boundaries. The parties have agreed that a "boundary" of an instruction group refers to the "beginning or end" of the group. The need for well-defined boundaries is exemplified by instructions such as SKIP and MICROLOOP, described in the specification. SKIP causes execution to advance to the beginning of the next instruction group (see id. at 14:19-24), while MICROLOOP causes execution to return to the beginning of the current instruction group. Id. at 24:1-16. Thus, the existence of well-defined instruction group boundaries is important to the execution of at least some of the instructions.
114. I believe that Plaintiffs' proposed construction captures these features of an instruction group.
115. I believe that Defendants' proposed construction introduces arbitrary limitations that are not supported by the specification or file history. Defendants agree with Plaintiffs that instruction groups are a "sets of from 1 to a maximum number of sequential instructions" and that each set is "provided to the instruction register as a unit."; But Defendants go on to introduce additional limitations that are clearly not required, namely that that "any operand that is present must be right justified" and that an instruction group "cannot encompass a single 32-bit RISC instruction."
116. I believe that right-justified operands are not required by the specification or the file history. It is true that the preferred embodiment includes certain instructions where the operands are right-justified in the instruction register, such as JUMP and IMMEDIATE (id. at 16:13-26), LOAD-SHORT-LITERAL (id. at 28:61-29:24), and FETCH-VIA-PC (id. at 26:66-27:14). But many of the instructions described will provide the claimed behavior even if operands are not always right justified as Defendants would require.
117. With regard to the exclusion of "a single 32-bit RISC instruction" as Defendants propose, I believe that this would do nothing to clarify the scope and meaning of "instruction groups." First, there is simply no basis for asserting that an instruction group cannot include a single 32-bit instruction. The specification provides examples of 32-bit instructions (e.g., BRANCH and CALL (id. at 20:41-42)), and where these instructions are used, a 32-bit instruction group would consist of a single instruction. These instructions were not disclaimed during prosecution; in fact, they were used as examples of the claimed subject matter. See, e.g.,Amd. 6/12/97, at 8-9, Ex. 14, Amd. 11/21/97 at 9, Ex. 16. So it is clear that some instruction groups can consist of a single 32-bit instruction.
118. Apparently realizing that they cannot simply exclude all single-instruction groups,Defendants rely on the qualifier "RISC" to identify the one-instruction group they propose to exclude. This identification, however, is unsatisfactory because it is both unclear and inconsistent with the disclosed embodiments of the claimed invention. The definition is unclear because it is not possible for one skilled in the art to determine with certainty whether a single instruction is or is not a "RISC instruction." As is known in the art, "RISC" stands for "reduced instruction set computer." '584, 1:13. The term refers to a design philosophy whose goals are to simplify microprocessor design by reducing the number of distinct instructions that a microprocessor needs to be able to execute. See, e.g., id. at 1:28-33. Thus "RISC" does not identify a specific instruction or format of instruction; instead, it describes an overall attribute of a microprocessor architecture. Because "RISC" applies to a processor's instruction set architecture considered as a whole, it does not make sense to speak of "a single 32-bit RISC instruction." Thus, saying that an instruction group "cannot encompass a single 32-bit RISC instruction," as Defendants propose, provides no guidance to the person having ordinary skill in the art as to what instructions might or might not be excluded from the scope of "instruction groups."
119. Moreover, excluding 32-bit RISC instructions from the scope of "instruction groups" would be contrary to the specification of the '584 patent. The instruction set presented therein could fairly be called a RISC instruction set, as it is includes a small number of instructions with simple formats. Indeed, the specification refers to the preferred embodiment as "a simplified, reduced instruction set computer (RISC) microprocessor."; Id. at 1:12-13. The preferred embodiment is characterized as a "RISC-influenced 32-bit CPU" (id. at 7:13-14) and in another place as being "like any RISC type architecture" (id. at 25:66). The preferred embodiment, consistent with the RISC design philosophy, supports a relatively small instruction set with a small number of instruction formats and simple decoding. As noted above, the instruction formats include a mix of 32-bit instructions and shorter instructions. Thus, the preferred embodiment includes some instruction groups that are "a single 32-bit RISC instruction." 120. The file history also provides no basis for excluding a 32-bit RISC instruction from the definition of "instruction groups." Defendants presumably believe they can justify this exclusion based on a statement in the file history referring to "typical RISC processors where all instructions are 32-bits regardless of the amount of information needed to actually describe the operation to be performed." Amd. 6/12/97 at. 9, Ex. 14 (emphasis added). But that statement is made to contrast the fixed-length instructions of "typical" RISC processors with the claimed approach, in which instruction bandwidth can be increased by "reducing the number of instruction bits required to perform the same operation" (id.), allowing shorter instructions to be used at least some of the time. Thus, at most, the statement in the file history is intended to distinguish instruction set architectures in which all instructions are 32 bits. Applicant did not exclude or disclaim architectures where the instruction set includes instructions of different lengths, some of which happen to be 32 bits.
121. For these reasons, I believe that a person of ordinary skill in the art would understand that "instruction groups" means "sets of from 1 to a maximum number of sequential instructions, each set being provided to the instruction register as a unit and having a boundary." Therefore, I believe that Plaintiffs' construction for this term is the correct one.
Disputed Term: "operand" Disputed Term Claims Plaintiffs Defendants operand 29 an input to an operation specified by an instruction that is encoded as part of the instruction an input to a single operation specified by an instruction that is encoded as part of the instruction where the size of the input can vary depending on the value of the input
122. I believe that Plaintiffs' definition reflects the intended scope of the term "operand" as used in the claims. In general, the term "operand" is used in the art to refer to input data for an operation to be performed by a microprocessor. Microprocessors can use many types of operands, as was correctly observed by Applicants during prosecution of the '584 patent. Amd. 11/21/97 at 8, Ex. 16. As further described by Applicants, operands can be classified by the technique used to locate them. For instance, operands can be "register-addressed,"; with the instruction encoding an identifier for the register that contains the operand. Operands can also be "memory operands," with the instruction specifying an address in memory at which the operand is stored. In this case, the address can be specified directly by encoding the address in the instruction or indirectly by encoding in the instruction an identifier of a register that contains the memory address of the operand. As Applicants stated during prosecution, operands can also be "'immediate operands,' that is operands that are encoded as part of the instruction." Id. In view of Applicants' following statement that immediate operands are "the only type of operands referred to" by the claims (id.), I conclude that it is correct to limit the meaning of operand to "an input to an operation specified by an instruction that is encoded as part of the instruction" as Plaintiffs propose.
123. Defendants propose to further limit "operand" to variable-width operands, i.e., to immediate operands "where the size of the input can vary depending on the value of the input." I believe that this is inappropriate because it is contrary to examples that Applicants expressly identified during prosecution as being within the scope of the claims. Specifically, in the final amendment, Applicants provided a list of "examples in the specification that support the claims as amended." Amd. 2/05/98 at 7, Ex. 17. These examples include FETCH-VIA-PC and LOADSHORT-LITERAL.
124. As defined in the specification, FETCH-VIA-PC fetches "the 32-bit memory content pointed to by the Program Counter" onto the parameter stack. '584, 26:66-27:1. "The effect is of loading a 32-bit immediate operand." Id. at 27:5-6. Thus, the immediate operand for a FETCH-VIA-PC instruction is fixed-width, not variable width.
125. Similarly, LOAD-SHORT-LITERAL is "used to push an 8-bit literal onto the parameter stack." Id. at 28:62-63. "Literal" as used in this context is widely recognized as a synonym for "immediate operand," and the operand in this case is also fixed-width. Defendants' proposed construction, which would exclude embodiments Applicants expressly described as being covered, is therefore unduly narrow.
126. For these reasons, I believe that a person of ordinary skill in the art would understand that "operand" means "an input to an operation specified by an instruction that is encoded as part of the instruction." Therefore, I believe that Plaintiffs' construction for this term is the correct one. Disputed Term: "said instruction groups include at least one instruction that, when executed, causes an access to an operand or an instruction or both" Disputed Term Claims Plaintiffs Defendants
said instruction groups include at least one instruction that, when executed, causes an access to an operand or an instruction or both 29 the instruction being executed causes the CPU to use an immediate operand or execute a second instruction which is not the next sequential instruction the instruction being executed causes the CPU to use data or execute a second instruction
127. As a preliminary matter, I note that this phrase should be understood to mean that there is at least one instruction in the processor's instruction set that has the behavior of "causing an access to an operand or instruction or both."; A person of ordinary skill in the art would understand that not all instructions in an instruction set have this behavior. For example,the '584 specification discloses a "DROP" instruction whose behavior is to "Pop the top item from the Parameter Stack and discard it." Id. at 28:18-19. In this case, the top item of the Parameter Stack would not be an operand since it is not an input to an operation; it is simply being discarded. Nor does the DROP instruction cause an access to an instruction, as the processor would simply proceed with the next sequential instruction after executing the DROP instruction.
128. I believe that Plaintiffs' proposed construction is correct because it properly incorporates the above-discussed limitation of "operand" in the claims to "immediate operand," as opposed to other types of data. Plaintiffs' proposed construction also properly captures the understood meaning in the art of "causes an access to an instruction."
129. In regard to causing an access to an operand, I have discussed above why "operand" as used in claim 29 should be limited to "immediate operand" despite the fact that the term has a broader meaning in the art. Defendants, despite proposing an even narrower definition for "operand" than did Plaintiffs, propose here that "an access to an operand" is synonymous with any use of data by the processor. This would encompass a number of instructions that used data other than immediate operands (e.g., data stored in registers of the
processor or retrieved from memory), and there is no basis for believing that Applicants intended the claims to cover instructions of this type.
130. In fact, the file history provides evidence to the contrary. As noted above, Applicants stated that "the only type of operands referred to are 'immediate operands.'" Amd. 11/21/97 at 8, Ex. 16. Any construction that ignores this explicit statement is flawed. Further, in explaining the meaning of an instruction that "causes access to an operand," Applicants cited as an example the LOAD-SHORT-LITERAL instruction. Id. at 9. This instruction causes access to an immediate operand, as explained in the '584 patent specification. See '584, 28:61-67. Thus, Plaintiffs' definition, which refers to using an immediate operand, is preferable to Defendants' overly broad definition.
131. Next, Plaintiffs' proposed construction states that the instruction to which access is caused is "not the next sequential instruction." This limitation reflects the understanding common to persons of ordinary skill in the art that not every program instruction causes access to another instruction, even though execution of one instruction is normally followed by execution of another.
132. Specifically, as is well known in the field of microprocessor design, program instructions are usually arranged sequentially in memory. After executing one instruction, the processor usually progresses to the next instruction in the sequence. This is reflected in the common notion of a "program counter" that is used to keep track of a current execution point in the program code; as each instruction is executed, the program counter is incremented to correspond to the next sequential instruction. The preferred embodiment described in the '584 patent specification operates similarly. As shown in Fig. 4, the program counter is implemented using a program counter 130 and a "micro" program counter 180. Program counter 130 provides the address of the next group of instructions to memory controller 118 so that the instruction group can be fetched into instruction register 108. '584, 6:20-22. Micro program counter 180 determines which byte of the instruction group currently in instruction register 108 is to be executed by controlling a multiplexer 170. Id. at 5:65-6:2. Although not explicitly stated, the well-known function of a multiplexer is to pass through one of a number of possible inputs based on a control signal, and it is clear that the micro program counter 180 is providing a control signal to multiplexer 170. Thus, in most cases, instruction will proceed from one instruction to the next sequential instruction. Those skilled in the art would not consider sequential execution as a case where one instruction causes the access to the next; instead, it is the ordinary incrementing of the program counter or micro program counter that causes the access.
133. "Causing an access to another instruction" would be reserved for the type of instructions referred to in the art as "control flow instructions." These are instructions that cause the processor to deviate from the normal behavior of incrementing the program counter or micro program counter. Typically, execution of such instructions involves replacing the program counter value with a different value. Often, control flow instructions are conditional. When a conditional control flow instruction is executed, the processor will test for the presence of a certain condition. Depending on the test result, the processor will either jump to a "target" location associated with the instruction (this is sometimes referred to in the art as "taking a branch") or continue to the next sequential instruction (referred to as "not taking the branch").
134. The file history indicates that Applicants intended to use "causes an access to an instruction" to refer to control flow instructions. As an example of this type of instruction, Applicants identified the SKIP instruction. Amd. 11/21/97 at 9, Ex. 16. As explained in the '584 patent specification, the SKIP instruction "will jump over the remaining one, two, or three 8-bit instructions in the instruction register 108 and cause the next four-instruction group to be loaded into the register 108." '584, 14:21-24. Thus, SKIP is a control flow instruction because it causes a deviation from the normal sequential execution of instructions. Like other control flow instructions, it can be conditional. See id. at 14:6-22.
135. Defendants' proposed construction is thus overly broad as it eliminates the distinction between control flow instructions, which can cause access to another instruction, thereby altering program flow, and other types of instructions that do not alter the program flow. Plaintiffs' proposed construction, which refers specifically to causing an access to "an instruction which is not the next sequential instruction," captures the concept of a control flow instruction, which I believe is what Applicants intended the claim to cover.
136. For these reasons, I believe that a person of ordinary skill in the art would understand that "said instruction groups include at least one instruction that, when executed, causes an access to an operand or an instruction or both" means "the instruction being executed causes the CPU to use an immediate operand or execute a second instruction which is not the next sequential instruction." Therefore, I believe that Plaintiffs' construction for this term is the correct one. Disputed Term: "said operand or instruction being located at a predetermined position from a boundary of said instruction groups" Disputed Term Claims Plaintiffs Defendants said operand or instruction being located at a predetermined position from a boundary of said instruction groups 29 the immediate operand or the instruction that is accessed has a position, relative to the beginning or end of the instruction group that includes the operand or instruction being accessed, that is determined based on a portion of an accessing instruction that identifies an
operation to be performed and without reference to operand or address bits in the accessing instruction the bits forming the accessed operand or instruction either begin or end at a position defined in relation to the boundaries of the instruction group in the instruction register rather than the currently executing instruction
137. For conciseness, I will refer to "the operand or instruction that is accessed" as the "target" of the instruction that causes the access. I will also refer to the instruction group that includes the target as "the target group"; and the instruction group that includes the instruction causing the access as "the accessing group." Also, as is usually done in the art, I will use the term "opcode" to refer to "the portion of an instruction that identifies the operation to be performed." The parties have agreed that "boundary of an instruction group"; refers to "beginning or end of an instruction group," and I will use these two phrases as synonyms.
138. The disputed claim language refers to the location of an instruction or operand that is being accessed. It requires that the operand or instruction being accessed is "located at a predetermined position from a boundary of said instruction groups." One important aspect of the disagreement between Plaintiffs and Defendants in regard to this term is whether this "predetermined position" should be defined "relative to the beginning or end of the instruction group that includes the operand or instruction being accessed," as Plaintiffs propose, or "in relation to the boundaries of the instruction group in the register," as Defendants propose.
139. The specification does not use the phrase "predetermined position from a boundary …" to describe instruction execution. Instead, the phrase was introduced during prosecution. Amd. 2/05/98 at 5, Ex. 17. In response to the Examiner's request to identify specification support for this phrase, Applicants cited numerous examples from the '584 patent specification, including SKIP, MICROLOOP, IMMEDIATE, BRANCH and CALL, FETCHVIA-PC, and LOAD-SHORT-LITERAL. Id. at 7-8. Applicants explicitly identified these instructions as "the examples in the specification that support the claims as amended." Id. at 7. In view of this statement, I believe that the correct interpretation of "predetermined position from a boundary" should read onto each and every one of these examples.
140. I have considered the applicability of Plaintiffs' and Defendants' proposed constructions to each of these examples and concluded that only Plaintiffs' proposed construction is consistent with all of these instructions as described in the specification. Thus, only Plaintiffs' proposed construction gives the claims the full scope to which they are entitled.
141. Some of the instructions cited as examples are consistent with either construction. For example, MICROLOOP and LOAD-SHORT-LITERAL each cause an access to an operand or "target" instruction that is located in the same instruction group as the MICROLOOP or LOAD-SHORT-LITERAL. As described in the '584 specification, MICROLOOP causes a conditional jump back to the beginning of the instruction group that contains the MICROLOOP.
'584, 15:51-57. In this case, the target group and the accessing group are the same, so both Plaintiffs' and Defendants' proposed definitions would apply. Similarly, LOAD-SHORTLITERAL pushes "the 8-bit value found in byte 4 of the current 4-byte instruction group onto the Parameter Stack." '584, 29:22-24. Again, the target group is the accessing group, so both proposed definitions apply.
142. However, this is not the case for some of the other instructions cited as examples, notably BRANCH. In these cases, the position of the target instruction is "predetermined" relative to the boundaries of the target group, but not relative to the accessing group.
143. In the case of BRANCH (or CALL), the specification indicates that the target instruction is always the first instruction in a group. "Branches and calls are made to 32-bit word boundaries." '584, 20:35-36. This implies that the implementation of BRANCH in the preferred embodiment includes resetting the micro program counter so that execution begins with the instruction on the boundary, which will be first in the instruction register once the group that contains the target is loaded. This counter reset happens based on the presence of the BRANCH opcode, regardless of the target address or other operand. Thus, consistent with Plaintiffs' construction, the branch target has a position, relative to the beginning or end of the instruction group that contains the target, which is determined from the opcode of the BRANCH instruction.
144. The implementation of BRANCH described in the '584 specification is not consistent with Defendants' proposed construction. Defendants assert that the target instruction would begin (or end) at a position defined in relation to "the boundaries of the instruction group in the instruction register," which apparently refers to the group that contains the BRANCH instruction. This is not the case. In the embodiment described in the '584 patent specification, the target group for a BRANCH instruction is identified using an address operand that is part of the BRANCH instruction. The address operand is interpreted at execution time to determine the address of the target group, and this address is loaded into the Program Counter. '584, 20:55- 22:5. Consequently, the target group (i.e., the group that contains the branch target) can be nearly anywhere in relation to the accessing group (i.e., the group that contains the BRANCH instruction), and there is no predetermined relationship between the two locations. Since Defendants' proposed construction is not consistent with the examples, I do not believe it is correct.
145. Defendants may attempt to support their proposed construction by reference to language in the prosecution history. For example, at one point, Applicants stated that "Neither [of two prior art references] teaches that the operand and instruction references made by instructions are located relative to the instruction group, rather than the executing instruction." Amd. 4/08/96 at 8, Ex. 13. Based on similarity of wording, this appears to be the basis for Defendants' proposed construction. But this statement is not specific as to whether the "instruction group"; relative to which references are made is the group in the register as Defendants propose or the target group as Plaintiffs propose. In addition, at the time this statement was made, the claims recited "… at least one instruction that accesses operands or instructions or both located relative to said instruction groups." Id. at 7, 8. The Examiner found this language to be insufficiently precise (Off. Action 8/22/97 at 2, Ex. 15), and Applicants subsequently introduced the more precise "predetermined position from a boundary" language (Amd. 2/05/98 at 5-6, Ex. 17), which Defendants' proposed construction apparently ignores.
146. Defendants may also point to a later statement from the file history that "One of the unique characteristics of the claimed processor and processing method is the locating of operands or instructions by their position within the current instruction group, a characteristic we call 'groupedness.'" Id. at 6. This language, however, would appear to apply only if the phrase "current instruction group"; is understood as the group that contains the target. Otherwise, it would not apply to instructions, such as BRANCH or SKIP. Since Applicants proceeded to cite SKIP and BRANCH, among others, as examples of the type of instruction being claimed (see id. at 7-8), I believe that this "groupedness" language is best understood as referring always to the target group, which either is current or becomes current during execution.
147. For these reasons, I believe that a person of ordinary skill in the art would understand that "said operand or instruction being located at a predetermined position from a boundary of said instruction groups" means "the immediate operand or the instruction that is accessed has a position, relative to the beginning or end of the instruction group that includes the operand or instruction being accessed, that is determined based on a portion of an accessing instruction that identifies an operation to be performed and without reference to operand or address bits in the accessing instruction." Therefore, I believe that Plaintiffs' construction for this term is the correct one. Disputed Term: "decoding said at least one instruction to determine said predetermined position" Disputed Term Claims Plaintiffs Defendants decoding said at least one instruction to determine said predetermined position 29 interpreting an instruction, in particular the portion thereof that signifies the operation to be performed, in order to identify a position relative to the beginning or end of the instruction group that includes the operand or instruction being accessed, without reference to operand or address bits in the instruction being interpreted interpreting an instruction, in
particular the portion thereof that signifies the operation to be performed, in order to identify a position relative to the beginning or end of the current instruction group 148. For conciseness, I will refer to this disputed term "the 'decoding' step."; The parties agree that the term "decoding" relates to "interpreting an instruction, in particular the portion thereof that signifies the operation to be performed," which is consistent with how the term is used in the art. "Decoding" an instruction generally refers to interpreting it into internal
control signals for the execution section of the microprocessor. See, e.g., '584, 6:3-4. As a rule, all portions of an instruction are decoded. In this case, however, the language of claim 29 states that the instruction is decoded "to locate said predetermined position." As described above, the "predetermined position" is intended to be always the same for instructions of a given type. See Amd. 2/05/98 at 7-8, Ex. 17. Since the opcode —the portion of the instruction that signifies the operation to be performed — is the portion of the instruction that is always the same, it follows that this portion should be the focus of the "decoding" step, as the parties apparently agree. 149. The crucial difference in the parties' proposed constructions for the "decoding" step reflects the difference in their respective views regarding the meaning of "predetermined position." Plaintiffs characterize the "decoding" step as identifying "a position relative to the beginning or end of the instruction group that includes the operand or instruction being accessed' (that is, the target), while Defendants characterize it as identifying "a position relative to the beginning or end of the current instruction group." As discussed above, I believe that Plaintiffs' proposed construction properly reflects the meaning of "said predetermined position." Plaintiffs' construction of the "decoding" step is consistent with this meaning. If the "predetermined position" is defined relative to the boundaries of the target group, it follows that the "decoding" step should identify that position.
150. Plaintiffs' proposed construction of the "decoding" step also emphasizes that the predetermined position is indentified "without reference to operand or address bits in the instruction being interpreted," which reflects the processor behavior described in the '584 specification. As noted above, an instruction can be thought of as having various discrete parts, including an opcode that identifies the operation the processor is to perform and some number of operand identifiers (which in the general case might be immediate operands, register identifiers, and/or memory addresses, as discussed above with reference to "operand"). See Amd. 11/21/97 at 8, Ex. 16. In response to a given opcode, the processor will always perform the same action, such as adding two operands, loading an operand into a register or onto a parameter stack, branching or jumping to a new point in the program code, and so on, even though the operand data may vary among instances of the same instruction. Thus, a particular opcode determines certain aspects of processor behavior but not all of them. Of interest here is the "predetermined position," which is identified without reference to operand or address bits as Plaintiffs' construction states.
151. This can be seen by reviewing the examples of instructions that claim 29 is intended to cover. See Amd. 2/05/98 at 7-8, Ex. 17. Consider, for instance, the SKIP instruction. When a SKIP instruction is encountered, assuming any condition is satisfied, the 2-bit microinstruction counter (labeled as 180 in Fig. 16 of the '584 patent) is reset to zero as the next instruction group is latched into instruction register 108. '584, 14:20-27. The resetting of the microinstruction counter causes execution of the next group to begin at the beginning boundary of the group, i.e., the "predetermined position" for a SKIP instruction. See Amd. 2/05/98 at 7, Ex. 17. Similarly, for a MICROLOOP instruction, if the loop counter is not zero, the 2-bit
microinstruction counter is cleared. '584, 14:54-57. Clearing the counter without loading a new group causes execution to return to the beginning boundary of the accessing group, i.e., the "predetermined position" for a MICROLOOP instruction. See Amd. 2/05/98 at 7, Ex. 17.
152. For a BRANCH instruction, the target is aligned at a 32-bit word boundary. '584, 20:35-36, 21:43-45. The target word is selected based on an operand, but since the target is predetermined to be aligned at the boundary, the microinstruction counter can be reset simply based on the fact that the opcode corresponds to the BRANCH opcode. Thus, the predetermined position, which in this case is the beginning boundary, is identified without reference to any operand.
153. The same principle applies where an operand is accessed. For example, in JUMP or IMMEDIATE instructions, the operand is "right justified in the instruction register. This means that the least significant bit of the operand is always located in the least significant bit of the instruction register." Id. at 16:15-18; Amd. 2/05/98 at 7, Ex. 17. The location of the operand relative to the end boundary can thus be determined based solely on the opcode, which indicates the presence of the operand. Similarly, for a LOAD-SHORT-LITERAL instruction, the operand is always in "Byte 4 of the current 4-byte instruction group." '584, 29:23-25.
154. As these examples show, the "predetermined position" for the accessing instruction is determined from the opcode, without reference to immediate operand or address bits in the instruction being determined. Plaintiffs' definition correctly describes the processor's behavior.
155. Defendants' proposed construction fails to correctly describe the behavior in all cases. In particular, Defendants' construction implies that the position of the target operand or instruction relative to the "current group"; — by which I presume they mean the accessing group — is determined from the opcode. In at least the case of a BRANCH, this is inaccurate. The position of the branch target relative to the accessing group is determined using an operand, (id. at 11:6-15, 20:55-21:21), not from the opcode alone. As already noted, there is no question that Applicants intended claim 29 to cover the BRANCH instruction. Amd. 2/05/98 at 7, Ex. 17; Amd. 11/21/97 at 9, Ex. 16. Since Defendants' proposed construction fails to cover this embodiment, I believe it is inaccurate. 156. For these reasons, I believe that a person of ordinary skill in the art would understand that "decoding said at least one instruction to determine said predetermined position" means "interpreting an instruction, in particular the portion thereof that signifies the operation to be performed, in order to identify a position relative to the beginning or end of the instruction group that includes the operand or instruction being accessed, without reference to operand or address bits in the instruction being interpreted." Therefore, I believe that Plaintiffs' construction for this term is the correct one. Disputed Term: "locating said predetermined position" Disputed Term Claims Plaintiffs Defendants locating said predetermined position 29 establishing operand or instruction supply within the instruction group that
includes the operand or instruction being accessed at the predetermined position using the results of the decoding step to ascertain the address of the accessed operand or instruction by
referencing the current instruction group address rather than the current executing instruction address without adding or subtracting an operand with the current Program Counter
157. For conciseness, I will refer to this disputed term as "the locating step.";
158. Plaintiffs' proposed construction flows from the construction of "predetermined position" and the "decoding" step discussed above, as well as the agreed-upon construction of the following "supplying"; step. The parties have agreed that the "supplying"; step refers to "using the result of the locating step in the step of transferring the bits forming the accessed operand or instruction to the CPU." Consistent with this, once the instruction has been decoded, the next logical step is to set up the instruction register to supply the target to the CPU. This corresponds to "establishing operand or instruction supply within the instruction group that includes the operand or instruction being accessed at the predetermined position." In some cases, such as the MICROLOOP and LOAD-SHORT-LITERAL instructions discussed above, the target instruction group is the accessing group, and establishing instruction supply at the predetermined position simply means setting the register such that the next transfer of bits to the CPU begins or ends at the predetermined position within the accessing group (e.g., by resetting the microinstruction counter as described in the '584 patent at 14:55-56). In other cases, such as the SKIP and BRANCH instructions discussed above, the target instruction group would need to be loaded into the instruction register in addition to setting the register such that the next transfer of bits to the CPU begins or ends at the predetermined position. See, e.g., id. at 14:24-29. Plaintiffs' definition is thus suitably broad to describe the possible actions that should be covered by "the locating step.";
159. Defendants' proposed construction is inaccurate. It refers to "ascertain[ing] the address of the accessed operand or instruction by referencing the current instruction group address rather than the current executing instruction address without adding or subtracting an operand with the current Program Counter." For instructions such as SKIP or FETCH-VIA-PC, this construction is questionable. SKIP and FETCH-VIA-PC each entail incrementing the program counter. Id. at 23:15-18, 27:10-14. This incrementing could be viewed as adding an operand to the program counter. The operand in this case would be a constant corresponding to the length of an instruction group (e.g., 1 word or 4 bytes) and need not be encoded in the instruction. However, it is not clear whether Defendants intend "an operand" in "without adding or subtracting an operand" to be limited to immediate operands, especially in light of Defendants' proposal to construe "causes access to an operand" as coextensive with "uses data.";
160. In the case of a BRANCH instruction, Defendants' construction simply does not apply. The '584 patent describes two embodiments that use different techniques for determining a branch target address. In a first embodiment, BRANCH instructions take a variable-length operand of 8, 16, or 24 bits. "The microprocessor 50 treats the three operands similarly by adding or subtracting them to the current program counter." Id. at 11:12-16. In a second embodiment, selected bits of the current program counter are combined with bits of the branch operand. In this embodiment, the selected bits of the current Program Counter are simply replaced by bits of the operand. Id. at 20:47-21:21. At the same time, the high-order bits of the program counter can be incremented, decremented, set to zero, or left unmodified. Id. at 21:9-15.
161. Defendants' construction is clearly contrary to the first embodiment, which specifically refers to "adding or subtracting [operand bits] to the current program counter." Id. at 11:12-16. Thus, the construction can only be justified if Applicants disclaimed this embodiment. But the specification and file history provide no evidence of a clear disclaimer. The only statement related to the merits of the two embodiments is an observation in the '584 specification that the second embodiment allows branches to execute faster than addition or subtraction. Id. at 20:43-53. Given that the same document includes an explicit description of a first embodiment that uses addition or subtraction (id. at 11:12-16), I can only conclude that this comparison was not intended as a disclaimer of the slower embodiment. The file history includes no further discussion of the relative merits of bit-replacement and arithmetic techniques. Thus, I believe that a proper construction should cover both embodiments, as Plaintiffs' does and Defendants' fails to do.
162. Furthermore, Defendants' construction is at least arguably inconsistent with the second embodiment. Replacement of bits is a different operation from addition or subtraction, but the second embodiment does include addition or subtraction in the high-order bits of the page count. As noted, these bits can be incremented, decremented or zeroed in response to the branch instruction. To control this aspect of branch behavior, the branch instruction includes a two-bit field (XX) that specifies whether to increment, decrement, zero or preserve the high-order bits of the program counter. Id. at 21:8-15. When increment or decrement is selected, a constant will be added to or subtracted from the program counter. Although the specification is not explicit on this point, addition or subtraction is generally necessary when incrementing or decrementing a multi-bit value. At the very least, some arithmetic is necessary to account for possible carries that may occur, e.g., when adding 1+1 in binary. Attempting to distinguish incrementing from adding is unhelpful in this case given that there is no evidence that making such a distinction is necessary. For these reasons, I believe that a person of ordinary skill in the art would understand that "locating said predetermined position" means "establishing operand or instruction supply within the instruction group that includes the operand or instruction being accessed at the predetermined position." Therefore, I believe that Plaintiffs' construction for this term is the correct one.



I declare under penalty of perjury under the laws of the United States of America that Alvin M. Despain for going is true and correct. EXECUTED this day of March, 2007.

CERTIFICATE OF SERVICE
I hereby certify that counsel of record who are deemed to have consented to electronic service are being served this 19th day of March, 2007, with a copy of this document via the Court’s CM/ECF system per Local Rule CV-5(a)(3). Any other counsel of record will be served by electronic mail, facsimile transmission and/or first class mail on this same date.
Roger L. Cook

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