The dynamic RAM has a refresh circuit with two operation modes. In the first operation mode, a variety of signals necessary for the refresh operation are formed in the dynamic RAM. Accordingly, the refresh operation of the dynamic RAM is performed completely automatically. As long as the refresh operation is being carried out, a busy signal is produced from the dynamic RAM to prevent an erroneous writing operation or reading operation. In the second operation mode, the refresh operation of the dynamic RAM is performed in synchronism with a starting signal supplied from an external unit. The busy signal produced by the dynamic RAM that is working under the first operation mode can be used as a starting signal for the dynamic RAM that is working under the second operation mode. Therefore, the refresh operation is effected in synchronism for the dynamic RAM's that constitute the memory system, and the through-put of the memory system is enhanced.

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor memory device and a system employing the same, and particularly to a dynamic random access memory (hereinafter referred to as dynamic RAM) and a system employing the same.

The dynamic RAM has a plurality of dynamic memory cells each consisting of a memory capacitor which stores data in the form of electric charge and an insulated gate field effect transistor (hereinafter referred to as MOSFET) which selects address. In the dynamic memory cell formed on a semiconductor substrate, the electric charge built up in the memory capacitor decreases with the lapse of time due to a leakage current. To store the correct data in the memory cells at all times, therefore, it is necessary to perform a so-called refresh operation according to which the data stored in the memory cells is read out before it extinguishes, the data is amplified and is written again onto the same memory cells.

For instance, the memory cells in a 64-kilobit dynamic RAM are refreshed by a refresh function which is disclosed in a journal "Denshi Gijutsu", Vol. 23, No. 3, Mar. 1, 1981 pp. 30-33. That is, the dynamic RAM is provided with an automatic refresh function which automatically refreshes a plurality of memory cells in the dynamic RAM by applying a refresh signal having a predetermined level to external terminals for refresh control, and is further provided with a self refresh function which performs the refresh operation every time a predetermined period of time has passed by maintaining the external refresh signal at a predetermined level to actuate a built-in timer circuit. This refresh system requires the external refresh signal and, hence, is not capable of performing a completely automatic refresh operation.

Another possible approach is to perform the self refresh operation every time a predetermined period of time set by a built-in timer circuit has passed. However, the inventors of the present invention have found that the above method develops a problem as described below. That is, in the case of a memory system consisting of a plurality of dynamic RAM's, the individual dynamic RAM's perform the refresh operation independently of each other. Therefore, through-put of the memory system decreases strikingly.

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