I have not read through all this yet. I think wolf may also have some details on this in his archives?

Claim 29 of the ‘584 patent is a method claim. It provides: In a microprocessor system including a central processing unit, memory, and an instruction register, a method for providing instructions and operands from said memory to said central processing unit comprising the steps of: providing instruction groups to said instruction register from said memory wherein certain of said instruction groups include at least one instruction that, when executed, causes an access to an operand or an instruction or both, said operand or instruction being located at a predetermined position from a boundary of said instruction groups; decoding said at least one instruction to determine said predetermined position; locating said predetermined position; and supplying, from said instruction groups, using the predetermined location, said operand or instruction or both to said central processing unit.

3. ‘584 Patent

“Instruction” means “a command to a processor that tells the processor what operation to perform.” “Boundary of said instruction groups” means “beginning or end of an instruction group.” “Supplying, from said instruction groups, using the predetermined location, said operand or instruction or both to said central processing unit” means “using the results of the locating step in the step of transferring the bits from the accessed operand or instruction to the central processing unit.” “Instruction register” means “a hardware element that receives and holds an instruction group as it is extracted from memory; the register either contains or is connected to circuits that interpret the instructions in the group.”

3. ‘584 Patent

a. “microprocessor”

The Court adopts its previous construction of this term in the ‘336 patent. See Section IV(B)(1)(b).

b. “central processing unit”

The Court adopts its previous construction of this term in the ‘336 patent. See Section IV(B)(1)(a).

c. “instruction groups”

The next term is “instruction groups.” The plaintiffs’ proposed construction is “sets of from 1 to a maximum number of sequential instructions, each set being provided to the instruction register as a unit and having a boundary.” The defendants propose “sets of from 1 to a maximum number of sequential instructions, in which the execution of the instruction depends on each set being provided to the instruction register as a unit and in which any operand that is present must be right justified and which cannot encompass a single 32-bit traditional conventional instruction.” The dispute is whether an operand that is present in the instruction group must be right justified and whether the instruction group may encompass a single 32-bit traditional conventional instruction. The plaintiffs contend that right justified operands are a feature of the preferred embodiment. The plaintiffs also argue that the claim language was broadened during prosecution history when the language “selecting, in accordance with position in said instruction register of one of said instructions of one of said instruction groups, an operand from said one of said instruction groups” was removed from the claim. Amendment, June 12, 1997, at 6. In addition, the plaintiffs point out that the specification includes 32-bit instructions. See ‘584 patent, 20:41-42. The defendants argue that the specification states that “operands must be right justified in the instruction register.” ‘584 patent, 16:15-16. In addition, the defendants argue that the applicants limited operands in this manner to overcome prior art rejections. See Amendment, June 17, 1997, at 13; Amendment, February 5, 1998, at 7. The defendants also contend that although the specification includes 32-bit instructions, the specification never identifies a single 32-bit instruction as instruction groups. According to the defendants, the specification defines “instruction group” as “being 8-bit and 16 or 24-bit instructions.” ‘584 patent, 23:4-7. The specification and prosecution history refer to the fact that operands in the instruction register must be right justified. The applicants, however, did not exclude a single 32-bit instruction as an instruction group. In a preferred embodiment, a microprocessor fetches instructions “in 32-bit chunks called 4-byte instruction groups” where an “instruction group may contain from one to four instructions.” ‘584 patent, 23:4-5, 19:18-19. If a 4-byte (or 32-bit) instruction group contains one instruction, then the instruction group may contain a single 32-bit instruction. The Court construes “instruction groups” to mean “sets of from 1 to a maximum number of sequential instructions, each set being provided to the instruction register as a unit and having a boundary, and in which any

operand that is present must be right justified.”

d. “operand”

The plaintiffs argue that the term means “an input to an operation specified by an instruction that is encoded as part of the instruction.” The defendants propose “an input to a single operation specified by an instruction that is encoded as part of the instruction where the size of the input can vary depending on the value of the input.” The plaintiffs argue that the defendants’ proposed construction would exclude a preferred

embodiment which includes fixed length operands. See ‘584 patent, 29:62-27:7. However, the plaintiffs appear to agree that the size of the input can vary. The intrinsic evidence does not show a clear limitation where the size of the input needs to

vary depending on the value of the input. The Court construes the term to mean “an input to a single operation specified by an instruction that is encoded as part of the instruction where the size of the input can vary.”

e. “said instruction groups include at least one instruction that, when executed, causes an access to an operand or instruction or both” The plaintiffs propose “the instruction being executed causes the CPU to use an immediate operand or execute a second instruction which is not the next sequential instruction.” The defendants’ proposed construction is “the instruction being executed causes the CPU to use data or execute a second instruction.” The main dispute is whether the second instruction can be the next sequential instruction. The plaintiffs argue that one of ordinary skill in the art would regard the normal program flow of going from one instruction to the next sequential instruction as “causing an access to an instruction.” The defendants contend that the specification describes a SKIP instruction where the second instruction accessed is the next sequential instruction. ‘584 patent, 23:12- In reply, the plaintiffs contend that claim 29 refers to control flow instructions, not ordinary instructions. The intrinsic evidence does not support the limitation proposed by the plaintiffs. Accordingly, the Court construes the term to mean “the instruction being executed causes the CPU to use an

operand or execute a second instruction.”

f. “said operand or instruction being located at a predetermined

position from a boundary of said instruction groups” The plaintiffs propose “the immediate operand or the instruction that is accessed has a position, relative to the beginning or end of the instruction group that includes the operand or

instruction being accessed, that is determined based on a portion of an accessing instruction that identifies an operation to be performed and without reference to operand or address bits in the accessing instruction.” The defendants propose “the bits forming the accessed operand or instruction either begin or end at a position defined in relation to the boundaries of the instruction group in the instruction register rather than the currently executing instruction.” The principal dispute is whether the instruction group refers to the group in which the currently executing instruction is located or whether it refers to the group in which the instruction or operand being accessed is located. The plaintiffs argue that, during prosecution, the applicants referred to the predetermined position of the accessed operand or instruction. See Supplemental Amendment, February 5, 1998, at 6-8. The plaintiffs also argue that instruction location is determined based on the particular place for instructions of that type. In addition, the plaintiffs contend that the target address specified by the instruction has no effect on the decision to begin executing at the beginning boundary of a target group. The defendants argue that the Abstract explains the meaning of this phrase. It states A high-performance microprocessor system using instruction that access operands and instructions located relative to the current instruction group rather than located relative to the current instructions, as is the convention, is disclosed herein. ‘584 patent, Abstract. The defendants also contend that the plaintiffs add limitations that are not supported by the intrinsic evidence. In reply, the plaintiffs contend that the term “current” in the Abstract refers to the target group, not the accessing group. For example, one of ordinary skill in the art would, in the case of a BRANCH instruction, determine the target instruction relative to the boundary of the target group, not the accessing group. A “predetermined position” refers to a position based on the instruction group being accessed. See ‘584 patent, 2:29-35. The Court construes the term to mean “the operand or instruction is accessed at a position defined in relation to the boundaries of the instruction group that includes the operand or instruction being accessed.”

g. “decoding said at least one instruction to determine said predetermined position” The plaintiffs contend that the term means “interpreting an instruction, in particular the

portion thereof that signifies the operation to be performed, in order to identify a position relative to the beginning or end of the instruction group that includes the operand or instruction being accessed, without reference to the operand or address bits in the instruction being interpreted.” The defendants propose “interpreting an instruction, in particular the portion thereof that signifies the operation to be performed, in order to identify a position relative to the beginning or end of the current instruction group.” The Court construes the term to mean “interpreting an instruction, in particular the portion

therefor that signifies the operation to be performed, in order to identify a position relative to the beginning or end of the instruction group that includes the operand or instruction being accessed.”

h. “locating said predetermined position”

The next term is “locating said predetermined position.” The plaintiffs argue that this term means “establishing operand or instruction supply within the instruction group that includes the operand or instruction being accessed at the predetermined position.” The defendants argue that the term means “using the results of the decoding step to ascertain the address of the accessed operand or instruction by referencing the current instruction group address rather than the current executing instruction address without adding or subtracting an operand with the current Program Counter.” The parties make similar arguments with regards to “predetermined position” as discussed in the previous section. The plaintiffs oppose the additional limitation in the defendants’ proposed construction of

“without adding or subtracting an operand with the current Program Counter.” According to the plaintiffs, this would exclude a preferred embodiment from the specification stating that the processor “treats the three operands similarly by adding or subtracting them to the current program counter.”

‘584 patent, 11:13-15. In support of this additional limitation, the defendants argue that additions and subtractions are done only at assembly/linking and not at run time. See ‘584 patent, 20:43-50. The defendants’ construction improperly incorporates a limitation from the preferred embodiment. The Court construes the term to mean “locating the operand or instruction within the instruction group that includes the operand or instruction being accessed at the predetermined position.”

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