I'm trying to understand the examiner's argument with respect to Kajiaya. Why are we having to argue it again?

Since it appears that the examiner has bought into the sequence of instructions for defining a processing unit, I think he is now arguing that, because Kajiaya instructions can be changed via different bonding and or masking combination, that is considered sequential instructions. Of course the change in instructions, I believe, are meant to address a different production run, not the same chips. Otherwise we are talking designing the chip one way and then changing the same chip. And I don't even think Kajiaya makes any reference to redoing previously designed chips, just indicates the choices available. Hard to fanthom why the examiner is intent on trying to make Kajiaya something that it is clearly not. Either he needs it, or is just wanting to frustrate the patent holder. I'm hoping it is the former.

GLTA, Opty