New Pacer--JOINT CASE MANAGEMENT CONFERENCE STATEMENT
[RELATED CASES]

UNITED STATES DISTRICT COURT
NORTHERN DISTRICT OF CALIFORNIA
SAN FRANCISCO DIVISION
ACER, INC., ACER AMERICA
CORPORATION and GATEWAY, INC.,
Plaintiffs,
v.
TECHNOLOGY PROPERTIES
LIMITED, PATRIOT SCIENTIFIC
CORPORATION, and ALLIACENSE
LIMITED,
Defendants.
Case No. 5:08-cv-00877 JW
HTC CORPORATION and HTC
AMERICA, INC.,
Plaintiffs,
v.
TECHNOLOGY PROPERTIES
LIMITED, PATRIOT SCIENTIFIC
CORPORATION, and ALLIACENSE
LIMITED,
Defendants.
BARCO N.V., a Belgian corporation,
Plaintiff,
v.
TECHNOLOGY PROPERTIES LTD.,
PATRIOT SCIENTIFIC CORP., and
ALLIACENSE LTD.,
Defendants.

JOINT CASE MANAGEMENT CONFERENCE STATEMENT
[RELATED CASES]

Date: October 3, 2011
Time: 10:00 a.m.
Dept: Courtroom 9, 19th Floor
Judge: Hon. James Ware
Case3:08-cv-05398-JW Document224 Filed09/26/11 Page1 of 13
The parties from the three above-captioned actions, Plaintiffs Acer Inc., Acer America
Corp., and Gateway, Inc. (collectively “Acer”), HTC Corporation and HTC America Inc.
(collectively “HTC”) and Barco, N.V. (“Barco”), and Defendants Technology Properties Limited
(“TPL”), Patriot Scientific Corporation, and Alliacense Limited (collectively “Defendants”),
respectfully submit this Consolidated Joint Case Management Conference Statement (“CMC
Statement”) pursuant to the Court’s Order Setting Case Management Conference issued on
September 8, 2011, which requires, inter alia, a brief description of the patents at issue, the
current status of the related actions, and the parties’ proposed schedule.
I. BRIEF DESCRIPTION OF PATENTS-IN-SUIT
Acer and HTC filed their respective declaratory judgment actions on February 8, 2008,
while Barco filed its declaratory judgment action on December 1, 2008 as follows:
(1) The Acer Action (Case No. 5:08-cv-00877);
(2) The HTC Action (Case No. 5:08-cv-00882); and
(3) The Barco Action (Case No. 5:08-cv-05398).
All three actions above were related and pending before Judge Fogel before their
reassignment to this Court. The four Patents-in-Suit in the Acer and HTC actions are U.S. Patent
Nos. 5,809,336 (the “’336 Patent”), 5,440,749 (the “’749 Patent”), 5,530,890 (the “’890 Patent”)
and 6,598,148 (the “’148 Patent”) (collectively “Patents-in-Suit”). Three of the four patents—
the ’336 Patent, the ’749 Patent, and the ’890 Patent—are at issue in the Barco action.
The four Patents-in-Suit, which share the same specification, are directed to different
aspects of a microprocessor system. Generally speaking, the ’336 Patent is directed to the
microprocessor system’s clocking mechanisms, while the ’749 and ’890 Patents are directed to
the microprocessor system’s architectural features. The ’148 Patent relates the microprocessor
system’s memory.
A. Plaintiffs’ Statement
1. Brief Description of the ’336 Patent
The ’336 Patent, entitled “High Performance Microprocessor Having Variable Speed
System Clock,” purports to describe the use of an on-chip first clock to time the CPU and a
second clock to time the input/output (I/O) interface.
According to the ’336 Patent, a CPU’s maximum allowable speed varies based on
environmental factor such as temperature, voltage and process (e.g., the higher the temperature,
the slower the CPU’s maximum allowable speed). To ensure the CPU always operates properly
in any environment, the traditional CPU clock is restricted at a sufficiently low speed such that it
would not exceed the CPU’s maximum allowable speed even in the worst environment.
The ’336 Patent claims that such restriction results in CPU “designs that must be clocked
a factor of two slower than their maximum theoretical performance, so they will operate properly
in wors[t] case conditions.” ’336 Patent, 16:50-53. To recapture the lowered CPU performance,
the ’336 Patent purports to provide an on-chip first clock whose speed varies based on
environmental factors such that it always clocks the CPU “at the maximum frequency possible,
but never too fast” under any environment. ’336, 16:54-17:10.
Because the I/O interface typically cannot operate at a variable speed, the ’336 purports to
provide a second fixed-speed clock to time the I/O interface. The purported use of the first onchip
CPU clock decoupled from the second I/O clock allows the two clocks to run without a
timing relationship (or “asynchronously”), freeing the on-chip first clock to time the CPU always
at its maximum allowable speed, which can vary higher or lower depending on the temperature,
voltage and process factors in the environment.
2. Brief Description of the ’148 Patent
The ’148 Patent, also entitled “High Performance Microprocessor Having Variable Speed
System Clock,” purports to describe a microprocessor that combines the on-chip first clock of the
’336 Patent with the use of more than 50% of the surface area of the microprocessor’s integrated
circuit for memory.
3. Brief Description of the ’749 Patent
The ’749 Patent, entitled “High Performance, Low Cost Microprocessor Architecture,”
purports to describe a microprocessor that fetches multiple instructions from memory and then
supplies them to the CPU in a single memory cycle. The ’749 Patent explains, however, that
“[t]he slowest procedure the microprocessor . . . performs is to access memory.” ’749 Patent,
22:14-17. “Memory is accessed . . . when instructions are fetched.” Id. “The bottleneck in most
computer systems is the memory bus. The bus is used to fetch instructions and fetch and store
data.” ’749 Patent, 5:54-56.
The ’749 Patent purports to address this “bottleneck” problem by fetching multiple
instructions from memory and supplying them to the CPU during “a single memory cycle,” i.e.,
the period of time required to perform one memory access. Because the CPU can execute
instructions much faster than it can fetch them from the memory, allowing multiple instructions to
be fetched and supplied to the CPU during a single memory cycle can supposedly improve
performance by permitting the fetching and execution of instructions to take place in parallel. See
’749 Patent, 22:17-40.
The ’749 Patent also includes claim limitations directed to a pushdown stack directly
coupled to the CPU’s arithmetic logic unit (“ALU”) such that explicit source and destination
addresses in the instructions are not required to transmit data to and from the ALU. These
limitations are consistent with the wires directly coupling the top two locations, i.e., the “top
item” and the “next item,” of the pushdown stack and the ALU, as shown in Figure 2 of the
’749 Patent.
4. Brief Description of the ’890 Patent
The ’890 Patent, entitled “High Performance, Low Cost Microprocessor Architecture,”
purports to describe a special stack architecture intended to allow faster access to certain memory
locations. The proposed special stack architecture is combined with other claimed features, such
as a separate direct memory access (“DMA”) CPU that allows the main CPU to off-load memory
transfer of data to the DMA CPU to improve the microprocessor system’s performance.
B. Defendants’ Statement
1. Background of the Technology of the ‘336 Patent
Microprocessors are complex machines, with millions of individual parts whose operation
requires coordination, both internally and with external components, for the chip to function
properly. This coordination is performed by clock signals. U.S. Patent No. 5,809,336 (“the ’336
Patent”), entitled “High Performance Microprocessor Having Variable Speed System Clock,”
teaches the use of two independent clocks in a microprocessor system – an on-chip first clock to
time the CPU, and a second independent clock to time the input/output (I/O) interface.
Decoupling the system clock from the I/O clock allowed the clocks to run independently (or
“asynchronously”), freeing the system clock, and thus the CPU, to run faster when needed (or
more slowly to conserve power). This decoupling had the added benefit of reducing the
sensitivity of the system as whole to temperature, voltage and manufacturing variations, since the
on-chip first clock and the CPU could vary together in response to such variations, with minimal
impact on the I/O interface due to the second clock domain.
2. Background of the Technology of the ’148 Patent
U.S. Patent No. 6,598,148 (“the ’148 Patent”) also entitled “High Performance
Microprocessor Having Variable Speed System Clock,” teaches a microprocessor that combines
the on-chip first clock of the ’336 patent with the use of more than 50% of the surface area of the
integrated circuit for memory.
3. Background of the Technology of the ’890 Patent
U.S. Patent No. 5,330,890 (“the ’890 patent”), entitled “High Performance, Low Cost
Microprocessor Architecture,” teaches a dual stack architecture and the use of stack pointers that
that can reference memory in any location to provide more architectural flexibility and faster
access to data elements. Combining this with other claimed features, such as a memory controller
and direct memory access, the ’890 Patent allows the CPU to off-load memory transfer of data to
achieve further efficiencies and higher performance.
4. Background of the Technology of the ’749 Patent
Microprocessors operate instructions that are usually stored in a memory that is slower
than the CPU. U.S. Patent No. 5,440,749 (“the ’749 patent,”), entitled “High Performance, Low
Cost Microprocessor Architecture,” teaches a processor that fetches multiple instructions at a
time, and then supplies them to the CPU in parallel (at the same time) in a single memory cycle.
Since memory is generally slower than the CPU, being able to fetch and supply more than one
instruction at a time increases the amount of instructions the CPU can receive in a given time, and
thus increases instruction bandwidth.
The ’749 Patent combines this technology with the last-in first-out data organization also
called a “pushdown stack.” A stack is an efficient way of organizing data in computer memory
that uses a last-in first-out data structure, and an intuitive way of organizing data for a processor
to perform arithmetic functions.
II. CURRENT STATUS OF THE CASE
A. Some Claim Terms of The Patents-In-Suit Were Previously Construed In
Earlier Litigation.
The ’336 and ’148 Patents were the subject of a prior litigation in the Eastern District of
Texas (terminated before the filing of the instant related actions in 2008), in which Judge John T.
Ward issued a claim construction order in mid-2007. Technology Properties Ltd. and Patriot
Scientific Corp. v. Matsushita Electric Industrial Co., Ltd., et al., No. 2:05-CV-494 (TJW). The
Patents-in-Suit have been the subject of multiple, now all terminated reexamination proceedings,
during which various claims have been cancelled, amended and added with additional prosecution
history developed after Judge Ward’s claim construction ruling.
 Plaintiffs contend that the amended or newly added claims have a substantially
narrower scope than that of the original claims in the Patents-in-Suit. All currently
asserted independent claims of the ’336, ’749 and ’890 Patents have been either
amended or newly added, and one out of three asserted independent claims of the
’148 Patent, expired in August 2009, has been cancelled.
 Defendants contend that not all of the asserted claims are amended and, where
claims have been amended or added, the amended and newly issued claims have
the same scope as the original claims in the Patents-in-Suit.
Judge Fogel stayed the three instant cases for a period of eight months from June 2009 to
February 2010 due to then still pending reexamination proceedings of the Patents-in-Suit. After
the stay was lifted, the parties began propounding discovery and proceeding with the claim
construction process. The parties filed their original Patent Local Rule 4-3 Joint Claim
Construction and Prehearing Statement on October 29, 2010 (“Original Statement”) (Acer Dkt.
203; Barco Dkt. 110; HTC Dkt. 189) and the parties completed claim construction briefing,
including surreply briefing, on no more than 30 claim terms on April 6, 2011.
B. The Markman Hearing Was Reset After New And Amended Claims Emerged
From Reexamination.
Before the scheduled May 10, 2011 Markman hearing could take place, claims in two of
the four patents-in-suit, U.S. Patent Nos. 5,440,749 (the “’749 patent”) and 5,530,890 (the “’890
patent”), were amended and added during reexamination proceedings. The Defendants
successfully moved to amend their infringement contentions to address the amended and
additional claims, and during a case management conference held on June 24, 2011, the Court set
a new date for the Markman hearing, and ordered supplemental claims construction briefing on
the new claim terms. The revised schedule was based upon the parties’ conditional stipulation to
allow time to address the amended infringement contentions so long as the claim construction
hearing were held before November 23, 2011, and the court accommodated the stipulation by
setting the Markman hearing date for November 14, 2011. The parties then met and conferred on
additional claim terms for construction in light of the amended infringement contentions, and on
August 23, 2011, submitted the Supplemental Joint Claim Construction and Prehearing Statement
Under Patent Local Rule 4-3 (Acer Dkt. 290; Barco Dkt. 210; HTC Dkt. 319). The cases were
subsequently reassigned due to Judge Fogel’s anticipated departure, which resulted in the vacatur
of the claim construction tutorial and hearing then scheduled for November 2011. No claim
construction brief had been filed before the case was reassigned and briefing schedule vacated.
III. PARTIES’ PROPOSED SCHEDULE
Depending on the Court’s availability, the parties propose that the Court select the date or
dates for the claim construction tutorial hearing to allow a briefing schedule of at least thirty-five
days. The Plaintiffs would like to seek the Court’s guidance as to its availability after December
19, 2011 or in January 2012 for the claim construction tutorial and hearing. The Defendants
request a claim construction tutorial and hearing in the second week of January or at the Court’s
earliest availability thereafter. Once the date or dates for the tutorial and hearing are set, the
parties will meet and confer to stipulate to a briefing schedule accordingly.

JOINT CMC STATEMENT -

IV. ADDITIONAL INFORMATION

A. LEGAL ISSUES

The principal legal issues that the Parties dispute are:
a. The construction of the claims of the Patents-in-Suit;
b. Whether the Plaintiffs infringe any of the Patents-in-Suit;
c. Whether any infringement by Plaintiffs, if proven, was willful;
d. Whether the Patents-in-Suit are invalid and/or unenforceable; and
e. The amount of damages, if any, due to Defendants and potential entry of an
injunction.

B. MOTIONS AND ANTICIPATED MOTIONS

HTC has filed a motion for partial summary judgment of non-infringement of the ’749,
the ’336 and the ’148 Patents on April 8, 2011. Doc. No. 293 (HTC Action). The briefing on this
motion has been completed but no hearings on this motion has been set. The motion remains
pending before the Court.
Barco previously filed a motion for summary judgment of noninfringement of the ’336
Patent on December 1, 2010. Judge Fogel subsequently denied the motion on March 8, 2011.
Plaintiffs anticipate filing one or more additional motions for summary judgment.
Defendants request the Court consider limiting the number of summary judgment motions that
each party can file to one apiece.
C. AMENDMENT OF PLEADINGS
The parties do not anticipate filing any further amended pleadings.
D. EVIDENCE PRESERVATION
All parties have been advised by their counsel to preserve all relevant evidence, including
electronically stored information, if any.
E. DISCLOSURES
The parties have complied with the initial disclosure requirements of Fed. R. Civ. P. 26.
F. CLASS ACTIONS
This is not a class action case.

G. RELATED CASES THAT HAVE BEEN RESOLVED

(1) The ASUSTeK Action (Case No. 5:08-cv-00884); and
(2) The Sirius Action (Case No. 3:10-cv-00816).
H. RELIEF
Plaintiffs seek a declaratory judgment against Defendants for non-infringement and
invalidity of the Patents-in-Suit. Defendants seek damages from patent infringement and
injunctions for the Patents-in-Suit.
I. SETTLEMENT AND ADR
The Parties have engaged in mediation, but have not settled the disputes to date. See Doc.
Nos. 33 and 50 (HTC Action).
J. CONSENT TO MAGISTRATE JUDGE FOR ALL PURPOSES
The Parties do not consent to have a magistrate judge conduct all further proceedings
including trial and entry of judgment. A declination to proceed before a Magistrate Judge for all
purposes was filed in the Acer/Gateway Action 5:08-cv-00877, and the HTC Action and Barco
Action have been deemed related cases. See Doc. No. 4 (Acer/Gateway Action).
K. OTHER REFERENCES
The parties do not believe that this case is suitable for reference to binding arbitration, a
special master, or the Judicial Panel on Multidistrict Litigation.
L. NARROWING OF ISSUES
The Parties will file one or more dispositive motions seeking to narrow the issues in this
case. The Parties anticipate filing one or more motions for summary judgment.
M. EXPEDITED SCHEDULE
The Parties agree that this case is not suitable for expedited handling.
N. TRIAL
The case will be tried to a jury. Plaintiffs expect the duration of the trial will depend on
numerous factors, including the dispositions of the pending and anticipated summary judgment
motions that cannot be determined at this stage of the proceedings.
O. DISCLOSURE OF NON-PARTY INTERESTED ENTITIES OR PERSONS
The Parties have filed Corporate Disclosure Statements pursuant to Fed. R. Civ. P. 7-1.
P. STATUS OF DISCOVERY
The parties have conducted claim construction discovery already and are engaged in fact
discovery. Defendants have also initiated discovery with a number of third-party suppliers,
including some foreign-based third-parties. Given the complexity of the issues in this case,
additional document and deposition discovery will be needed after the issuance of the claim
construction order in this case. The parties have previously agreed to close fact discovery six
months after the final invalidity contentions are due, which must be served 50 days after the
issuance of the claim construction order. See, e.g., Dkt. 288 (in Acer action).
Q. OTHER MATTERS
There are no other matters that the parties believe need to be addressed at this time.
Respectfully submitted,
[SIGNATURE BLOCKS START ON THE NEXT PAGE]