<They are separate patents dealing with totally different things.>

I disagree and will be willing to go into further detail if necessary.

5,784,584 - Claim 2

The microprocessor system of claim 1 wherein said instruction decoding means further includes means, responsive to a SKIP instruction in said instruction register, for configuring said instruction fetching means such that the next instruction group is supplied to the instruction register, and for configuring said instruction supplying means to supply in succession from said instruction register, said sequential instructions, beginning with the first instruction in said instruction register from said next instruction group, to said central processing unit, and in which said means for generating counter control signal, also in response to the SKIP instruction, supplies the counter control signal to reset said counter to zero.

5,440,749 - Claim 5

The microprocessor system of claim 1 additionally comprising an instruction register for the multiple instructions connected to said means for fetching instructions, means connected to said instruction register for supplying the multiple instructions in succession from said instruction register, a counter connected to control said means for supplying the multiple instructions to supply the multiple instructions in succession, means for decoding the multiple instructions connected to receive the multiple instructions in succession from the means for supplying the multiple instructions, said counter being connected to said means for decoding to receive incrementing and reset control signals from said means for decoding, said means for decoding being configured to supply the reset control signal to said counter and to supply a control signal to said means for fetching instructions in response to a SKIP instruction in the multiple instructions.