I attemped to classify all of the terms being disputed by importance under each patent. I also classified the proposed claim construction terms by each party with either T3 or TPL. The 336 is the first patent and the non-controllable and variable based on the temperature, voltage and process parameters are THE most important issues for the 336. If those are included in Judge Ware's claim construction, we lose the 336. If they are excluded, we win the 336. All of the subsequent terms after "Ring Oscillator" are principally dependent upon the noncontrollable term. If the ring oscillator is non-controllable, then their can't be a timing relationship in the chip. "Providing an Entire Variable Speed Clock Disposed Upon Said Integrated Circuit Substrate" is possibly subject to the non-controllable term as it is included in the T3 definition. So "Operates Asychronously To" would by default fall to the T3 due to the non-controllable term. "Clocking Said Central Processing Unit" would be another casualty of the non-controllable term. If their is no control then the CPU will run at the fastest possible speed without running so fast it breaks but can't be controlled. That is essentially the core argument there. The "As a Function of Parameter" portion is not relevant imo.

Personally, I think TPL fully wins the 336 but I am a layman and do not know how the court will rule based on all of the legal issues and technical arguments.

The 749's first two items I believe are the most important for the 749 are "Instruction Register" and "Multiple Sequential Instructions". I will leave it up to others to comment on that. I would love for someone to tell us if there is a lynchpin holding together the 749. It would be nice if a proxy for PTSC would elaborate on this post and tell us if there is a core piece of technology that would torpedo the 749 if we do not get our proposed claim construction. I think I know but I am not 100% certain and would welcome clarification.

The following is the list and comments / corrections welcome.

336

G. The Proper Construction of “Ring Oscillator” (’336, ‘148, ’890, ’749 Patents).

T3:an oscillator having a multiple, odd number of inversions arranged in a loop, wherein the oscillator is: (1) noncontrollable; and (2) variable based on the temperature, voltage, and process parameters in the environment

TPL:an oscillator having a multiple, odd number of inversions arranged in a loop

H. The Proper Construction of “Providing an Entire Variable Speed Clock Disposed Upon Said Integrated Circuit Substrate” (’336 Patent).

T3:providing an entire variable speed clock disposed upon said integrated circuit substrate providing a variable speed clock that is located entirely on the same semiconductor substrate as the CPU and does not directly rely on a command input control signal or an external crystal/clock generator to generate a clock signal, wherein the variable speed clock is: (1) noncontrollable; and (2) variable based on the temperature, voltage, and process parameters in the environment

TPL:providing a variable speed system clock that is located entirely on the same semiconductor substrate as the CPU and does not directly rely on a command input control signal or an external crystal/clock generator to generate a clock signal

D. The Proper Construction of “Operates Asynchronously To” (’336 Patent).

T3:operates without a timing relationship to/with

TPL: timed by independent clock signals

F. The Proper Construction of “Clocking Said Central Processing Unit” (’336 Patent).

T3:timing the operation of the CPU such that it will always execute at the maximum frequency possible, but never too fast

TPL:timing the operation of the CPU

J. The Proper Construction of “As a Function of Parameter Variation” (’336 Patent).

T3:as a function of parameter variation in a determined functional relationship with parameter variation

TPL:based on parameter variation

749

C. The Proper Construction of “Instruction Register” (’749 and ’890 Patents).

T3:register that receives and holds one or more instructions for supplying to circuits that interpret the instructions, in which any operand that is present must be right-justified in the register

TPL:register that receives and holds one or more instructions for supplying to circuits that interpret the instructions

A. The Proper Construction of “Multiple Sequential Instructions” (’749 Patent).

T3:Two or more instructions in program sequence, in which any operand that is present must be right-justified in the instruction register

TPL:Two or more instructions in a program sequence

E. The Proper Construction of “Supply the Multiple Sequential Instructions to Said Central Processing Unit Integrated Circuit During a Single Memory Cycle” (’749 Patent).

T3:provide the multiple sequential instructions in parallel (as opposed to one-by-one) to said central processing unit integrated circuit during a single memory cycle without using a prefetch buffer or a one-instruction-wide buffer that supplies one instruction at a time

provide the multiple sequential instructions in parallel to said central processing unit integrated circuit during a single memory cycle

TPL:supply the multiple sequential instructions to said central processing unit integrated circuit during a single memory cycle

I. The Proper Construction of “Push Down Stack Connected to Said ALU” (’749 Patent).

T3:a push down stack comprising a top item register and a next item register, both directly coupled to the ALU such that the source and destination addresses are not used

TPL:data storage elements organized to provide last-in first-out access to items connected to convey signals to a digital circuit that performs both arithmetic and logical operations.

890

B. The Proper Construction of “Separate Direct Memory Access Central Processing Unit” (’890 Patent).

T3:a separate CPU that fetches and executes instructions for performing direct memory access without using the main CPU

TPL:electrical circuit for reading and writing to memory that is separate from a main CPU