http://photos.imageevent.com/banos/t3/First%20Claim%20Const%20Order%206%2012%2012.pdf

Construction Claims:

Ware's construed definitions

[my thoughts]

From Ease's previous post:

The following is the list and comments / corrections welcome.

336

G. The Proper Construction of “Ring Oscillator” (’336, ‘148, ’890, ’749 Patents).

T3:an oscillator having a multiple, odd number of inversions arranged in a loop, wherein the oscillator is: (1) noncontrollable; and (2) variable based on the temperature, voltage, and process parameters in the environment

TPL:an oscillator having a multiple, odd number of inversions arranged in a loop

[needs further delineation]

H. The Proper Construction of “Providing an Entire Variable Speed Clock Disposed Upon Said Integrated Circuit Substrate” (’336 Patent).

T3:providing an entire variable speed clock disposed upon said integrated circuit substrate providing a variable speed clock that is located entirely on the same semiconductor substrate as the CPU and does not directly rely on a command input control signal or an external crystal/clock generator to generate a clock signal, wherein the variable speed clock is: (1) noncontrollable; and (2) variable based on the temperature, voltage, and process parameters in the environment

TPL:providing a variable speed system clock that is located entirely on the same semiconductor substrate as the CPU and does not directly rely on a command input control signal or an external crystal/clock generator to generate a clock signal

Ware: Providing a variable speed clock that is located entirely on the same semiconductor substrate as the central processing unit.

D. The Proper Construction of “Operates Asynchronously To” (’336 Patent).

T3:operates without a timing relationship to/with [appears to have chosen]

TPL: timed by independent clock signals

Ware: the timing control of the central processing unit operates independently of and is not derived from the timing control of the input/output interface such that there is no readily predictable phase relationship between them.

F. The Proper Construction of “Clocking Said Central Processing Unit” (’336 Patent).

T3:timing the operation of the CPU such that it will always execute at the maximum frequency possible, but never too fast

TPL:timing the operation of the CPU [appears to have been chosen]

Ware: providing a timing signal to said central processing unit.

J. The Proper Construction of “As a Function of Parameter Variation” (’336 Patent).

T3:as a function of parameter variation in a determined functional relationship with parameter variation

TPL:based on parameter variation [ I think chosen]

Ware: The disputed issue is whether the phrase requires a mathematical type predetermined functional relationship. Upon review, the Court finds that a person of ordinary skill in the art reading the patent would understand that the phrase “as a function of” is describing a variable that depends on and varies with another. Because neither the written description nor the prosecution history provide a basis for concluding that the phrase should be limited to a narrower definition of an exact mathematical type functional relationship, the Court declines to do so. Having resolved the only dispute tendered with respect to this phrase, the Court declines to construe it further.

749

C. The Proper Construction of “Instruction Register” (’749 and ’890 Patents).

T3:register that receives and holds one or more instructions for supplying to circuits that interpret the instructions, in which any operand that is present must be right-justified in the register

TPL:register that receives and holds one or more instructions for supplying to circuits that interpret the instructions [possibly chosen]

Ware: Because the Court finds that the language of the claim has been used with its plain and ordinary meaning, the Courtdeclines to further construe it

A. The Proper Construction of “Multiple Sequential Instructions” (’749 Patent).

T3:Two or more instructions in program sequence, in which any operand that is present must be right-justified in the instruction register

TPL:Two or more instructions in a program sequence

E. The Proper Construction of “Supply the Multiple Sequential Instructions to Said Central Processing Unit Integrated Circuit During a Single Memory Cycle” (’749 Patent).

T3:provide the multiple sequential instructions in parallel (as opposed to one-by-one) to said central processing unit integrated circuit during a single memory cycle without using a prefetch buffer or a one-instruction-wide buffer that supplies one instruction at a time

provide the multiple sequential instructions in parallel to said central processing unit integrated circuit during a single memory cycle

TPL:supply the multiple sequential instructions to said central processing unit integrated circuit during a single memory cycle [appears to have been chosen]

Ware: , the Court finds that this phrase is composed of commonly used words that have a plain and ordinary meaning. There is nothing in the claim or written description that would lead a person of ordinary skill in the art to conclude that the inventors intended to use the phrase with anything other than its plain and ordinary meaning. In particular, the Court finds that the word “multiple” would have been understood, by a person of ordinary skill in the art, to mean “two or more,” while the phrase “sequential instructions” would have been understood to mean “computer instruction in a sequential order.” Therefore, at this time, the Court declines to use any different words or phrases to construe the phrase “multiple sequential instructions.”

I. The Proper Construction of “Push Down Stack Connected to Said ALU” (’749 Patent).

T3:a push down stack comprising a top item register and a next item register, both directly coupled to the ALU such that the source and destination addresses are not used

TPL:data storage elements organized to provide last-in first-out access to items connected to convey signals to a digital circuit that performs both arithmetic and logical operations.

Ware: a last-in-first-out data storage element connected to the arithmetic logic unit.

890

B. The Proper Construction of “Separate Direct Memory Access Central Processing Unit” (’890 Patent).

T3:a separate CPU that fetches and executes instructions for performing direct memory access without using the main CPU

TPL:electrical circuit for reading and writing to memory that is separate from a main CPU

Ware: a central processing unit that accesses memory and that fetches and executes instructions directly, separately, and independently of the main central processing unit.