The company I work for blocks file sharing sites so I was not able to read the Markman that BaNoss kindly posted for everyone to read until this evening when I returned home from work, which is the reason I wanted to know the case # so I could look up the Markman on PACER. The Markman is not under the HTC Corporation nor the Barco cases. I suppose it is under Acer, but I didn't try that one. Anyhow, I have the case # number now ...

The following post is my laymans take on the Markman result. I have not consulted my EE contact as he is in Maine and I will speak to him tomorrow, although I probably won't be able to discuss with him at length the issues until he comes back from his trip. I would also defer to Laurie's contact as he attended the Markman and has much closer knowledge of the MMP and can place the arguments within context of TPL/PTSC's legal strategy.

The following is the list of T3 & TPL disputed terms with the Judge's final definition. I believe we did well, but there are footnotes in the claim construction that leave the door open for the Judge to make changes for the 749 and 336, although IMO he could've originally ruled against us and left the door open to amend the other way. So as I see it the fact that he ruled in our favor 100% for the 749 on virtually everything is good news. Time will determine if the 749 will be successfully monetized.

The two terms that are ambiguous to me are the "Separate Direct Memory Access Central Processing Unit" (Patent 890) and the "Operates Asynchrounously To" (Patent 336). Both constructions Judge Ware chose are not clear and concise. IMO there is room to argue both sides so I don't know how the constructions will be resolved at trial if we go that far.

The "Ring Oscillator" (Patent 336) was a surprise to me. Apparently the T3 argued persuasively and Judge Ware requires further information on a Voltage Controlled Oscillator and how it differs from a Ring Oscillator. Judge Ware stated in his claim construction,

The Court has examined the Talbot patent. Although the component is, indeed, referred to as a “voltage-controlled oscillator,” declarations and other extrinsic materials that have been tendered during the claim construction proceedings call into question the validity of the inventors’ contention to the PTO and to this Court that the “ring oscillator” is different from the “voltage-controlled oscillator” disclosed in Talbot. On the one hand, the Court has received extrinsic evidence that the voltage-controlled oscillator disclosed in Talbot is a ring oscillator. On the other hand, arguments have been submitted claiming that the voltage-controlled oscillator of Talbot is not a ring oscillator.37

37 This issue is important to claim construction, because it is relevant to understanding in

what manner the ring oscillator is “non-controllable,” as distinguished from the voltage-controlled oscillator disclosed in Talbot. Resolving this conflict might affect how the Court approaches issues with respect to the validity of the patent claim at issue.

Apparently TPL is going to have to argue convincingly how a Voltage Controlled Oscillator (VCO) referenced in Talbot during the reexamination of the 148 patent is not a ring oscillator. Judge Ware wants to know more about what was said to the reexaminer who, in his examination summary filed in the PAIR system at the USPTO, stated TPL said a ring oscillator is distinguishable over Talbot's VCO because it is non-controllable and varies based on temperature, voltage, and process parameters in the environment (the ring oscillator variable speed system clock is taught in the 336 but also referenced in the 148). So hopefully our lawyers can explain to Judge Ware (or the other judge) without disavowing anything, or rendering a portion of the 336 invalid. It looks like from the above statement in italics Judge Ware is questioning the validity of the 336 and it is within his power to rule a portion of the 336 invalid. IMO we should bring our A game to the briefing.

All of the above information is worth the time it took anyone to read it. The list below is how I scored the 10 disputed terms. Red is a win for TPL. The rest I said Don't Know in green and the ring oscillator is Further Briefing Needed in blue. Enjoy...lol

G. The Proper Construction of “Ring Oscillator” (’148, ’336, ’890, ’749 Patents). Further Briefing Needed

T3:an oscillator having a multiple, odd number of inversions arranged in a loop, wherein the oscillator is: (1) noncontrollable; and (2) variable based on the temperature, voltage, and process parameters in the environment

TPL:an oscillator having a multiple, odd number of inversions arranged in a loop

Judge:Further Briefing Needed

H. The Proper Construction of “Providing an Entire Variable Speed Clock Disposed Upon Said Integrated Circuit Substrate” (’336 Patent). TPL Win

T3:providing an entire variable speed clock disposed upon said integrated circuit substrate

providing a variable speed clock that is located entirely on the same semiconductor substrate as the CPU and does not directly rely on a command input control signal or an external crystal/clock generator to generate a clock signal, wherein the variable speed clock is: (1) noncontrollable; and (2) variable based on the temperature, voltage, and process parameters in the environment

TPL:providing a variable speed system clock that is located entirely on the same semiconductor substrate as the CPU and does not directly rely on a command input control signal or an external crystal/clock generator to generate a clock signal

Judge:Providing a variable speed clock that is located entirely on the same semiconductor substrate as the central processing unit.

D. The Proper Construction of “Operates Asynchronously To” (’336 Patent). The term “operates asynchronously to” is found in claims 11, 13 and 16 of the ’336 patent. Don’t Know

T3:operates without a timing relationship to/with

TPL: timed by independent clock signals

Judge:the timing control of the central processing unit operates independently of and is not derived from the timing control of the input/output interface such that there is no readily predictable phase relationship between them.

F. The Proper Construction of “Clocking Said Central Processing Unit” (’336 Patent). TPL Win

T3:timing the operation of the CPU such that it will always execute at the maximum frequency possible, but never too fast

TPL:timing the operation of the CPU

Judge: providing a timing signal to said central processing unit

J. The Proper Construction of “As a Function of Parameter Variation” (’336 Patent). TPL Win

T3:as a function of parameter variation in a determined functional relationship with parameter variation

TPL:based on parameter variation

Judge:As a Function of Parameter Variation

A. The Proper Construction of “Multiple Sequential Instructions” (’749 Patent). TPL Win

T3:Two or more instructions in program sequence, in which any operand that is present must be right-justified in the instruction register

TPL:Two or more instructions in a program sequence

Judge:“multiple sequential instructions.”

C. The Proper Construction of “Instruction Register” (’890 and ’749 Patents). TPL Win

T3:register that receives and holds one or more instructions for supplying to circuits that interpret the instructions, in which any operand that is present must be right-justified in the register

TPL:register that receives and holds one or more instructions for supplying to circuits that interpret the instructions

Judge: “Instruction Register”

E. The Proper Construction of “Supply the Multiple Sequential Instructions to Said Central Processing Unit Integrated Circuit During a Single Memory Cycle” (’749 Patent). TPL Win

T3:provide the multiple sequential instructions in parallel (as opposed to one-by-one) to said central processing unit integrated circuit during a single memory cycle without using a prefetch buffer or a one-instruction-wide buffer that supplies one instruction at a time

provide the multiple sequential instructions in parallel to said central processing unit integrated circuit during a single memory cycle

TPL:supply the multiple sequential instructions to said central processing unit integrated circuit during a single memory cycle

Judge:“…Configured and Connected to … Supply the Multiple Sequential Instructions to Said Central Processing Unit Integrated Circuit During a Single Memory Cycle”

I. The Proper Construction of “Push Down Stack Connected to Said ALU” (’749 Patent). TPL Win

T3:a push down stack comprising a top item register and a next item register, both directly coupled to the ALU such that the source and destination addresses are not used

TPL:data storage elements organized to provide last-in first-out access to items connected to convey signals to a digital circuit that performs both arithmetic and logical operations.

Judge: “a last-in-first-out data storage element connected to the arithmetic logic unit”

B. The Proper Construction of “Separate Direct Memory Access Central Processing Unit” (’890 Patent). Don’t Know

T3:a separate CPU that fetches and executes instructions for performing direct memory access without using the main CPU

TPL:electrical circuit for reading and writing to memory that is separate from a main CPU

Judge:a central processing unit that accesses memory and that fetches and executes instructions directly, separately, and independently of the main central processing unit.