Sorry, I couldn't copy/paste the entire document. Here are the good parts

1. The Staff’s Construction is Consistent with the Plain Language of the

Claims, the Intrinsic Record of the '336 Patent, and Prior Markman

Orders

The specification of the '336 patent describes an embodiment of a microprocessor system

usingclocking techniques that overcome prior art limitations requiring that clock speeds be

restricted based on worst-case conditions. JXM-0001, '336 patent, at col. 15:44-53. According

to the patent:

The microprocessor 50 uses the technique shown in Figs. 17-19 to generate the

system clock and its required phases. Clock circuit 430 is the familiar “ring

oscillator” used to test process performance. The clock is fabricated on the same

silicon chip as the rest of the microprocessor 50.

Id. at col. 16:54-58. Although the disclosed clocking technique purportedly allows a

microprocessor to be clocked at optimal speed, the specification does not express a clear intent to

so limit the claims. See id. Based on the disclosure, it is possible for a designer to vary clock

speed by changing the number of inverters used in the ring inverter. See JXM-0001, '336 patent,

at Fig. 18. This disclosure is consistent with the construction proposed by TPL and the Staff, and

adopted by Judge Ware in Markman Order II. See SXM-0002, App., Tab. 2, Markman Order II,

at 0045-46. Moreoever, the plain language of the claim does not require or even suggest that the

CPU must be clocked at the maximum speed possible. Instead, the speed of the disclosed clock

is dependent on the propagation delay of the ring oscillator. Should too few inverters be used,

the clock would oscillate too fast, and should too many inverters be used, the microprocessor

would operate sub-optimally. In light of the plain language of the claim and the intrinsic

evidence, the Staff’s proposed construction is thus correct.

2. Respondents’ Proposed Construction is Flawed

Respondents’ construction, in contrast, attempts to import limitations from a disclosed

embodiment into the claims. Such a construction is improper in the absence of an expression of

intent by the patentee. Phillips, 415 F.3d at 1323; Vitronics, 90 F.3d at 1582-83; Markman, 52

F.3d at 979-80; Intel Corp. v. U.S. International Trade Commission, 946 F.2d at 836 (“Where a

specification does not require a limitation, that limitation should not be read from the

specification into the claims.”).

Respondents contend that “clocking said central processing unit” should be construed to

mean “timing the operation of the CPU such that it will always execute at the maximum speed

possible, but never too fast.” In this regard, the specification describes an optimal CPU clock

scheme such that “CPU 70 will always execute at the maximum frequency possible, but never

too fast.” JXM-0001, '336 patent, at col. 17:1-2. Moreover, the specification states that usingconventional clock schemes, microprocessors “must be clocked a factor of two slower than their

maximum theoretical performance, so they will operate properly in worse case conditions.” Id.

at col. 16:50-53. But while the '336 patent describes a design that purports to operate at the

maximum frequency possible, the Staff does not believe that the intrinsic evidence shows an

express intent to import this limitation. See Thorner v. Sony Computer Entertainment America,

LLC, 669 F.3d 1362, 1368 (Fed. Cir. 2012) (“Thorner”) (“It is … not enough that the only

embodiments, or all of the embodiments, contain a particular limitation. We do not read

limitations from the specification into claims; we do not redefine words.”). Thus, Respondents’

proposed construction is improper.

3. Conclusion

For at least these reasons, the Staff respectfully submits that the phrase “clocking said

central processing unit” should be interpreted to mean “providing a timing signal to said central

processing unit.”