The below link goes back to Judge Ware's claim constructions in California, which I also copied and pasted underneath the link. It is just fascinating to me that we requested one set of terms in front of Judge Ware and entirely separate terms at the ITC for essentially the same meanings. The reason I believe we sought different claim constructions at the ITC is based off of how the Respondents are trying to frame the arguement for non-infringement, which is to argue that all chips require and offchip crystal clock to clock the microprocessor. I'm not sure I buy that but I'm not the Judge or an expert. So we change our claim proposals to argue against their attempted framing of the argument. We'll see soon enough.

http://agoracom.com/ir/patriot/forums/discussion/topics/535545-my-laymans-take/messages/1691443

G. The Proper Construction of “Ring Oscillator” (’148, ’336, ’890, ’749 Patents). Further Briefing Needed

T3:an oscillator having a multiple, odd number of inversions arranged in a loop, wherein the oscillator is: (1) noncontrollable; and (2) variable based on the temperature, voltage, and process parameters in the environment

TPL:an oscillator having a multiple, odd number of inversions arranged in a loop

Judge:Further Briefing Needed

H. The Proper Construction of “Providing an Entire Variable Speed Clock Disposed Upon Said Integrated Circuit Substrate” (’336 Patent). TPL Win

T3:providing an entire variable speed clock disposed upon said integrated circuit substrate

providing a variable speed clock that is located entirely on the same semiconductor substrate as the CPU and does not directly rely on a command input control signal or an external crystal/clock generator to generate a clock signal, wherein the variable speed clock is: (1) noncontrollable; and (2) variable based on the temperature, voltage, and process parameters in the environment

TPL:providing a variable speed system clock that is located entirely on the same semiconductor substrate as the CPU and does not directly rely on a command input control signal or an external crystal/clock generator to generate a clock signal

Judge:Providing a variable speed clock that is located entirely on the same semiconductor substrate as the central processing unit.

D. The Proper Construction of “Operates Asynchronously To” (’336 Patent). The term “operates asynchronously to” is found in claims 11, 13 and 16 of the ’336 patent. Don’t Know

T3:operates without a timing relationship to/with

TPL: timed by independent clock signals

Judge:the timing control of the central processing unit operates independently of and is not derived from the timing control of the input/output interface such that there is no readily predictable phase relationship between them.

F. The Proper Construction of “Clocking Said Central Processing Unit” (’336 Patent). TPL Win

T3:timing the operation of the CPU such that it will always execute at the maximum frequency possible, but never too fast

TPL:timing the operation of the CPU

Judge: providing a timing signal to said central processing unit

J. The Proper Construction of “As a Function of Parameter Variation” (’336 Patent). TPL Win

T3:as a function of parameter variation in a determined functional relationship with parameter variation

TPL:based on parameter variation

Judge:As a Function of Parameter Variation

A. The Proper Construction of “Multiple Sequential Instructions” (’749 Patent). TPL Win

T3:Two or more instructions in program sequence, in which any operand that is present must be right-justified in the instruction register

TPL:Two or more instructions in a program sequence

Judge:“multiple sequential instructions.”

C. The Proper Construction of “Instruction Register” (’890 and ’749 Patents). TPL Win

T3:register that receives and holds one or more instructions for supplying to circuits that interpret the instructions, in which any operand that is present must be right-justified in the register

TPL:register that receives and holds one or more instructions for supplying to circuits that interpret the instructions

Judge: “Instruction Register”

E. The Proper Construction of “Supply the Multiple Sequential Instructions to Said Central Processing Unit Integrated Circuit During a Single Memory Cycle” (’749 Patent). TPL Win

T3:provide the multiple sequential instructions in parallel (as opposed to one-by-one) to said central processing unit integrated circuit during a single memory cycle without using a prefetch buffer or a one-instruction-wide buffer that supplies one instruction at a time

provide the multiple sequential instructions in parallel to said central processing unit integrated circuit during a single memory cycle

TPL:supply the multiple sequential instructions to said central processing unit integrated circuit during a single memory cycle

Judge:“…Configured and Connected to … Supply the Multiple Sequential Instructions to Said Central Processing Unit Integrated Circuit During a Single Memory Cycle”

I. The Proper Construction of “Push Down Stack Connected to Said ALU” (’749 Patent). TPL Win

T3:a push down stack comprising a top item register and a next item register, both directly coupled to the ALU such that the source and destination addresses are not used

TPL:data storage elements organized to provide last-in first-out access to items connected to convey signals to a digital circuit that performs both arithmetic and logical operations.

Judge: “a last-in-first-out data storage element connected to the arithmetic logic unit”

B. The Proper Construction of “Separate Direct Memory Access Central Processing Unit” (’890 Patent). Don’t Know

T3:a separate CPU that fetches and executes instructions for performing direct memory access without using the main CPU

TPL:electrical circuit for reading and writing to memory that is separate from a main CPU

Judge:a central processing unit that accesses memory and that fetches and executes instructions directly, separately, and independently of the main central processing unit.