on this but given some of the statements by Jim O, he says the PLLs keep the ring oscillator's speed within a range, although while it is in that range, the oscillator is dependent upon process, temperature and the source voltage (not control voltage). So I believe we are arguing that while the ring oscillator is in the acceptable range of operation, it is running as it was originally intended. I've confirmed this with my EE contact although short of seeing how the chips work and the engineering schematics, it is speculative. If this is an accurate interpretation, the judge would have to buy that argument. We are splitting hairs and hopefully the prior art chips, which were strictly controlled and varied directly proportionally due to the strict control of the external crystal, will be taken into consideration given their age - mid 1980s.