I agree in general but the argument again is how variable is the ring oscillator. There is a "dead band" in which the ring oscillator is susceptible to PVT in a PLL sysyem. The argument is whether or not that dead band is enough within a PLL. The PLL is essential to minimize the quantity of variability in a ring oscillator due to PVT so the on chip clock can communicate offchip and there is predictability there so both on and off chip clocks and signals can sychronize. The PLL does not remove the PVT variability completely. The big companies admit that. The big companies argue the variability is so small that does not matter and therefore is de minimis (legal term) and does not meet the standard to prove infringement. So the big companies argue, for example, a 300 megahertz clock's variability is only 300.01 megahertz. We argue the 0.01 variability in the clock is enough to prove infringement. If you magnify that variance it comes down to 30 or 300 kilohertz. In terms of a 360 degree phase relationship between the crystal reference clock nd the ring oscillator, it is about 1 or 2 degrees. Is that enough? Is the legal threshold of de minimis going to affect our chances? I don't know.