Startup moment when power is on (to supply voltage to PLL and external crystal) is either a dead zone moment or a similar moment that is a 366 event, IMHO. Logically speaking, since the clocking rate of the external crystal is 100 times slower comapre to the ring occilator inside PLL, at startup, ring occilator can occilators many times before the first control signal generated by external crystal/PLL arrangement. Unless PLL can delay the power supply to RO and stop RO to clock CPU, I don't see defendant can get arround 366 patent. Anyone see Pacer documents that discuss the delay of power at power on moment?
Again, I'm not an EE. My previous posting about this was deleted by a hub leader.
Do I need to be a EE to join the discussion?
