I agree. We are getting pretty close in understanding 336 in context of current litigation. Since the external criystal clock is running in very slow speed compare to ring oscillator, there is no way it can generate clock signal to CPU. Its fuction in accused products is to send a reference frequency to PLL, PLL rasie it 100 times and use it to compare with the frequency of the ring oscillator (the clocking rate generated by ring oscillator). If the ring oscillator is running too fast (temprature is high for example), of the VCO/PLL reduce the voltage to slow the ring oscillator. The oppiside is also true. The source of the clocking signal supplied to CPU is always the ring oscillator - it is the sole clocking originator. What the external criystal clock is doing is to provide a referrence signal for control (voltage) to slow down/speed up ring oscillator.

I think at the start, VCO/PLL is not in control - ring oscillator start to run according to PVT. after the first control by the VCO/PLL, VCO/PLL only control at times when ring oscillator is either running too fast or too slow (fixing). In between are dead zones (they buffer). Comments welcome.