< at STARTUP of these systems the RING OSCILLATOR GENERATES the CPU CLOCK SIGNAL WITHOUT the pll being engaged.>

What is the basis for your understanding of the above?

IMO, There is no question that at start up (min voltage) the RO oscillates at some frequency. That is not in doubt. But when you state that it generates the cpu clock, that entails that the signal is allowed to travel to the cup w/o being locked by the PLL.

It is my understanding that HTC is arguing that only PLL Locked signals are allowed to go to the cpu. All other signals are blocked. I certainly have no idea whether that is in fact their argument, nor do I know if it is true. I'm trying to accurately define what HTC's argument is with respect to start up. If anyone has a good handle on it, please chim in

Thanks

Opty