BERKELEY, Calif.--It`s not easy to get hardware designers and software developers in sync when it comes to developing a new computer architecture, according to Dave Patterson, one of the pioneers of the original RISC architecture.

The hardware takes years to develop, and work on affiliated software doesn`t start in earnest until the hardware is done. Simulators exist, but the software developers really don`t take advantage of them like they should, Patterson said. That causes the development cycle to drag out even longer.

Enter RAMP, or Research Accelerator for Multiple Processors. The idea behind the program is to build a laboratory computer out of field programmable gate arrays, reprogrammable chips that can be reconfigured to act as different chips. (As one Intel researcher has described it, the FPGA is the utility infielder of the semiconductor world.) Ideally, an FPGA-based RAMP computer could be assembled cheaply and easily.

``If you can put 25 CPUs in one FPGA, you can put 1,000 CPUs in 40 FPGAs,`` Patterson said during a symposium here this week at UC Berkeley, where he is a professor of electrical engineering. Such a computer would cost about $100,000, he estimated. It would also take up relatively little space--about one-third of a rack--and consume only about 1.5 kilowatts of power.

An equivalent computing cluster would cost about $2 million, take up 12 racks and consume 120 kilowatts.

The idea for a RAMP computer, which came up in a hallway conversation at a conference in 2004, is moving toward reality. A version with eight compute modules will be completed in the first half of this year, and the full 40-module version could come out in the second half of next year, Patterson said. Joining UC Berkeley in the project are researchers at Stanford University, the Massachusetts Institute of Technology and other schools.

``What we are not trying to do is build an FPGA supercomputer,`` Patterson said. ``What we are trying to do is build a simulator system.

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