Green88 wrote:

"That statement attributed to Dr. Taylor in the PCWorld article regarding 200nm feature size has been troubling my subconscious ever since I first read it. I originally chocked it up to either a misquote by the author of the article or maybe the good doctor just misspoke and didn't catch his mistake. It just doesn't make sense with everything we've learned about the technology so far. There are multiple sources for references to feature sizes of poet and speed that I recall. Here's one from the Toronto presentation. http://m.youtube.com/watch?feature=relmfu&v=NH9yj3u5Nig Just go to 5:56 in the clip to listen to Lee Shepherd talk about the speed of Dr Taylor's first chips he produced from about 3 years ago. Green"

I have to admit I didn't pick up on the discrepancy when I first read this article. Do you think there's a difference between individual transistor speed and the speed at which the processor as a whole would operate using complementary logic? Maybe scaled down n-channel trasistors operate at something 450GHz max, while the p-channel will be something like 12GHz (guess). So maybe the whole PET processor operates at some lower speed, limited by the p channel. I'm asking because otherwise the quotes in the PCWorld article are internally incoherent.

FTA:

http://www.pcworld.com/article/2033671/breaking-moores-law-how-chipmakers-are-pushing-pcs-to-blistering-new-levels.html

"OPEL only recently exited the R&D stage and hasn't tried to make itty-bitty transistors at Ivy Bridge's 20nm size, but the company claims that at 800nm, gallium arsenide processors are faster than today's silicon and use roughly half as much voltage.

"If you wanted to match the speed of today's silicon processors, at roughly a 3GHz clock rate, you wouldn't have to go all the way down to 20 or 30 nanometers," says OPEL chief scientist Dr. Geoffrey Taylor. "Heck, you could probably hit that at 200nm." And that's using planar technology, not 3D transistors."

These two paragraphs are right next to eachother and yet they seem to contradict eachother. I'd really like to get to the bottom of this because I still really don't understand how the lower clock rate of the p channel affects the overall performance of the processor. I wish someone could explain it because the NRs sometimes omits the p channel clock rate and only report the n channel. I also distinctly recall Jianhong Cai saying that the p channel rate didn't matter, but I admit I haven't had the patience to listen through the recording again to hear that statement another time. I also bring this up becasue the article below seems to suggest that the p channel (hole mobility) is a challenge facing those who wish to use GaAs to replace CMOS.

http://www.compoundsemiconductor.net/csc/features-details/19732104/Is-nanometer-scale-III-V-CMOS-cool-enough-to-rejuvenate-Moore%E2%80%99s-Law.html

"Dealing with the holes

Most III-Vs have very high electron mobilities, making them ideal for n–channel devices. But CMOS needs p-channel transistors too, and the hole mobility for III-Vs is too low - for many arsenides, it is actually lower than it is for silicon. Mobilities in silicon have improved through the addition of strain in the material, with the performance of the pchannel now approaching that of its n-type cousin. It will be interesting to see if the same trick will work for the arsenides."

I'm thinking that POET has some sort of "trick" to limit the effect of the reduced hole mobility, but I can't find what it is.

I also noticed that while POET has been reducing the n-channel gate length over time (to at least the 800nm lenght in the PCWorld article) they haven't been shinking the p channel, contrary to an earlier post of mine. To my knowledge the p channel remained at 1um in all published NRs.