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"No Liquidity event? Pushing mile stones, Why do we need 100nm? is that the largest chip size being used out there today?"
I'm not worried about these things and here's why:
No Liquidity event? Who says? I know it isn't being published in the CO or the MD&A's anymore, but they never said it isn't happening.
Remember: they are now actively engaging in negotiations with established players. The information we are getting from the company at this moment could very well be for the benefit of the negotiations more than for keeping us informed. If POET can make the convincing argument they willing to tough it out via a licensing route rather than a total sale, the big players under this impression will have to pony up to make it worth selling out.
MB was heard to say he wasn't expecting another AGM. Copetti has been quoted saying that "[He doesn't] think it’s much time before a much bigger player comes along and says to us ‘We want this and we don’t want anyone else to have it.’”. This sounds like a liquidity event is still on the horizon.
Furthermore, the last MD&A explicitly stated that they want to list on a US exchange. Given that they are already on a US exchange I surmise they are thinking more along the lines of NASDAQ. I believe that CC once commented here that our "exit strategy" could occur at the moment POET becomes a money making operation and switches to a less ridiculous exchange. To me, this might mean we get bought out for new shares and/or cash, with the potential that POET will IPO on the NAS. This scenario would qualify as a liquidity event, but to me this scenario poses a high risk of us losing a major portion of the value of POET in the shuffle between the buyout offer and the new listing. Anyone with personal experience with something like this please share because I've never been involved in such a transition.
As for the necessity for shrinking to the 100nm range, I think it's pretty straight forward. At 100nm in GaAs the performance is expected to surpass CMOS at 20nm, and more importantly, remains extensible for many more years. GaAs and Si gates are like apples and oranges. My understanding is that Si CMOS can achieve a higher density than GaAs ever will. But each transistor made in GaAs just runs circles around Si transistors, so with POET you don't need the same density to outperform high end CMOS.
Another factor that must have an impact is the diameter of the wafers. GaAs wafers are too brittle to go much past ~200mm. Si goes to 450mm. Lots more area on Si wafers compared with GaAs wafers. However, with fewer POET chips required - one to be exact - I'm sure the industry could make due with fewer chips per wafer. |
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