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Message: p-channel info

I've been in contact with IR and I got some technical details that I can share that folks might find interesting. Also, It has become clear that the 100nm is definitely in response to a request from someone interested in POET. I thought I was impressed with POET before. But Taylor and his team seem to have been able to do something that nobody thought was possible!

The reason I got IR involved can be understood after reading a post by Green88 and my reply to him:

http://agoracom.com/ir/POETTechnologies/forums/discussion/topics/584117-100nm/messages/1832439#message

http://agoracom.com/ir/POETTechnologies/forums/discussion/topics/584117-100nm/messages/1832619

Also, I summarized what I thought was the importance of the 100nm goal here:

http://agoracom.com/ir/POETTechnologies/forums/discussion/topics/585830-intel/messages/1837961#message

From the post:

"... the electron mobility is multiples higher in GaAs than it is in Si. I believe this means that equivalent transistors in Si and GaAs will have dramatically different clock speeds with GaAs coming out on top.

....Now, if you read the whole chart you might have noticed that the hole mobility is another story (third row). This is a known hurdle for the proliferation of III-V based transistors.

This has been the only unanswered question for me and I currently have a request in to IR to explain this. POET has reported the n-channel clock speed in the high 30s and low 40s. The p-channel hasn't been reported as often and is only ~3GHz. Also, the n-channel has shrunk since the laser announcement while the p-channel remains 1um.

I hope to hear back soon and I hope to hear that POET's "secret sauce" is that the very low hole mobility has either been increased beyond what is known to be possible (such as what Si achieved according to this article). Or even better, I would like to discover that the p-channel speed has become a non issue due to the construction of POET complementary inverters. In other words, I hope they can confirm that the n-channel speeds are the ones that compare to CMOS."

So, here's what I asked and a paraphrase of the response I got:

"OPEL only recently exited the R&D stage and hasn't tried to make itty-bitty transistors at Ivy Bridge's 20nm size, but the company claims that at 800nm, gallium arsenide processors are faster than today's silicon and use roughly half as much voltage.

"If you wanted to match the speed of today's silicon processors, at roughly a 3GHz clock rate, you wouldn't have to go all the way down to 20 or 30 nanometers," says OPEL chief scientist Dr. Geoffrey Taylor. "Heck, you could probably hit that at 200nm." And that's using planar technology, not 3D transistors"

Both statements are true (I'll write about the seeming discrepancy between the two paragraphs next). The reason why POET can outperform CMOS with seriously different feature sizes comes down to heat. POET's GaAs transistors don't have an issue with waste heat and so the clock frequency can be much higher. This is something we knew already, but I thought I'd confirm it.

Unless I'm misreading it or neglecting a detail, the first paragraph suggests that POET is faster than Si chips at 800nm, but the second seems to suggest that we need to shrink past 200nm to be competitive. Which of these two gate sizes match/surpass current silicon processors?

This answer has to do with the two types of tranistors needed to make the complementary inverter that was recently demonstrated. What CMOS and POET complementary inverters have in common is that when the p and n are paired together, current can't pass through (and be constantly wasted) because they are opposites - current can only pass briefly when both the p and n are in the act of switching. This is why CMOS has been so dominant for so long. Current doesn't flow continuously so it is very power efficient.

Now this is the exciting part. POET is powerful and unique because they have found a way to increase the "hole mobility" (the way p-channel transistors carry current) in a way that nobody else has been able to do. This is why PET is special. GaAs has always had super fast n-channel transistors available, but only Taylor and team has been able to make the other half of the pair work fast enough to battle Si CMOS. Now I understand why Lee S spoke more highly of the transistor accomplishment than even the laser (which we were all so excited about) at the second meeting in TO.

So as to the discrepancy, I think (IR couldn't disclose anything not publicly available so I don't have a complete answer) the p-channel is the key and when we hit <200nm both the p- and n- channels will far surpass Si to the point where it is economical to make the switch to POET

Finally in a related question, the following article suggests that GaAs has very poor "hole mobility" which I gather impacts the p-channel:

http://www.compoundsemiconductor.net/csc/features-details/19732104/Is-nanometer-scale-III-V-CMOS-cool-enough-to-rejuvenate-Moore%E2%80%99s-Law.html

"Dealing with the holes

Most III-Vs have very high electron mobilities, making them ideal for n–channel devices. But CMOS needs p-channel transistors too, and the hole mobility for III-Vs is too low - for many arsenides, it is actually lower than it is for silicon."

I suppose this is where the proprietary aspect of POET comes in, but if possible, I'd like to know if part of POET's charm is that it manages to "Deal with the holes" as the article suggests. I don't have to know how it works (although I wouldn't mind if it was explained) but just if this issue is addressed by POET's unique process.

Again, the p-channel is the key. I wan't told how it all works (proprietary/material) but I was assured that what makes POET special is that their solution to "the problem" of holes in GaAs is what makes PET a breakthrough.

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