Thanks oogee for all the info.

You weren't kidding about getting old watching that video. I actually couldn't stand to watch it. That could be in part because it was just repeating info I'd already learned from some of my various DD sessions.

Like you I spent some time looking into the various differences between N and P - type transistors and how they work together in CMOS.

I found a really good primer on transistors here:

http://www.youtube.com/watch?v=IcrBqCFLHIY

I like his videos. He has a good way of taking a complicated concept and laying it out in an easy to digest manner without dumbing it down too much, with a sense of humor too.

Anyway I sometimes get sidetracked while searching for info and the rest of this post is just some of my thoughts that some may find interesting.

I got to thinking after reading about CMOS and single channel transistors about the importance of the complimentary channels being achieved with POET and PET. With POET being the first time a p-channel has been created with GaAs, I wonder how much of the energy savings that have been claimed can be attributed to just the CMOS achievement.

Mobile devices today already use GaAs chips. Now here is where I'm going to make a few logical leaps and without actually researching it. I'm just going to say it and remain open to correction or confirmation. If POET is the first with CMOS using GaAs then the mobile GaAs chips in use today are either n-type or p-type(feel free to correct me). Those that have researched it know that n-type and p-type transistors drain energy constantly while running as opposed to CMOS which only draws significant energy to switch. So even with a constant drain of energy(my assumption) GaAs is still the material of choice over CMOS in Silicon for mobile devices.

Hope everyone can follow what I meant there. I guess the point I want to make is I am curious to know what portion of reported energy savings is attributed to CMOS vs the electron mobility of GaAs. I'm thinking that it must be significant because of the excitement showed by Lee S. as reported by oogee.

In the end it might not matter how fast the p-channel is able to run. It's main purpose may be to reduce energy consumption. Could that be why they haven't been reducing it's feature size with the n-channel features? From what I've read, the n-channel transistors in silicon run 2 - 3 times faster than same sized p-channel transistors (one source said "2.5-3 times" and another source said "2-3.4 times"). It seems p-channel transistors are typically made wider to account for this so the switch will be balanced for speed in both directions. This is what I have read.

My thoughts regarding this are, Do the n-channel and p-channel have to be balanced? Can most of the processing be done with the n-channel, and the p-channel can be used to process, yes, but mainly just be there to oppose the n-channel and provide the benefits of the CMOS architecture (that said , the p-channel's latest reported speed is still close to being just as fast as todays fastest silicon devices)? If CMOS requires the channels to be balanced (and I really have no knowledge regarding this whatsoever. Logical leaps, remember?), could Dr. Taylor have found a way to make it work in an unbalanced state?

I know this may be way out in left field for some of you but I really am getting tired of reading about the stock price. I'm looking forward to the time when deals are signed and more of the details of the technology can be released. I think there are many great days ahead. We only need patience.

Have a great weekend, everyone.

Green

P.S. I must have missed something. Who trademarked "Patience"? :)