What I find even more thrilling is this slide:
It shows the cost per wafer as a function of time and structure size ("process"). With smaller structures you can pack more transistors on a single wafer, which is nice. However, as the curves show, the smaller the structures are the more expensive the wafers get. And this wafer price increase "washes away the scaling benefit." In other words: Even if you can reduce the structure sizes, you won't gain any yield from doing so.
POET promises a way out: tremendous performance improvements without reducing structure size to uneconomic levels. The 100 nm milestone should demonstrate that.
Andrea