sula, that was a bit harsh*.

that JH has taken the time to share his opinion in a more rational way has value.

his most recent post here does more than blurt out koans; much better than what first landed as a pile of narcissistic-Oracle's opinion enshrined as fact earlier (which is what put me off in the first place)

I think we can have a rational, healthy discussion.

I do agree with you that external source references could bolster his case, however, there *are* points he raises which might be worth looking into, if only to dispel them.

Put aside for a moment that Taylor & BAE teams may have already overcome challenges such as these.

From the adoption perspective, an understanding of the generally *perceived* weaknesses lends some insight into what PC & Co. might face.

here's what comes to mind, re points 1-2-3.

a) GaAs ingots ... how much of a factor is this in reality? Oogee started looking at this a while back. We understand from his examination there's comfortably enough raw material to produce GaAs, however I don't recall it going deeper than that.

There was a degree of reliance on POET's cost comparison (the $15 vs. $200 ... FJ has the chart). Does the cost comparison stand?

As for purity (qv. yield), JC talked about it in one of the 2011 clips, I don't think there's been mention of it since. Which could be good or bad (is no news good news?).

b) scaling: JH allowed for an argument of n-1 (40nm). if it's sufficient to go one step further, being n-2 (90nm) then the point is moot (MS8 gets us there).

*is* n-2 sufficient? will a design fit into a given size? there is a reason somebody asked PTK to get to that node size. so we can speculate, without being heretical, that n-2 is indeed sufficient.

also, re die-size vs space availability: how much of this is this mitigated (i) by power (especially in the mobile space) ... would it make sense that if the ginormous battery can get smaller, then the die can get bigger, and (ii) by space provided by eliminating unnecessary chip-chip (etc) interconnects in a monolithic platform. don't know ... which leads into the next item ...

as to "everything must be redesigned" ... that's what TDK's are *for* (imo). how much of a hurdle is this, really? ask a few fab design techs (which I'm not). questions like these are possibly why fabs spend gobs and gobs of money on ECAD software for all the workflows; it's not like they have to lay out circuits by hand anymore.

c) this would be resolved by the expected named-partner PDA announcement.

Bravo JH, for beginning to articulate a skeptic's position in a more reasonable manner.

GLTA,

R.

* - yes. pot, kettle, black. sorry.