Aiming to become the global leader in chip-scale photonic solutions by deploying Optical Interposer technology to enable the seamless integration of electronics and photonics for a broad range of vertical market applications

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As far as I believe to understand it, the process is as such:

  1. BAE System produced the POET chips with the help of POET engineers who explained to the BAE engineers how to do it, how to deploy what is called the POET process.
  2. The TDK documentation explains the same to "current and potential custumers and partners", but not through engineers, but in the form of a written document. That is, if you want to produce POET chips in your garage fab, all you need is the TDK documentation. However, you still have to bother with all the nitty-gritty details yourself, which is a tedious and error-prone task. Anyway, everything you need of today's PET/POET ecosystem is in the TDK documentation.
  3. The TCAD models for PET (due end of Q3 2014) will greatly help in chip design, because they will provide PET components modelled in software. That means, you will have a library of pre-fabricated building blocks or templates, which you can pick, put in into place and parameterize as needed. Much, much easier than 2.!
  4. At a later point in time TCAD models will be available not only for PET but for the whole POET ecosystem. Here we don't have a milestone yet. – BTW, this explains what seemed to be a contradiction between MS 11 ("Full POET TDK") now and MS 12 ("PET Elektrical TDK") only in Q3: The milestones should be read MS 11 ("Full POET TDK Documentation") now and MS 12 ("PET Elektrical TDK Models") later. The milestone plan has it correctly, but the typography is suboptimal.

Disclaimer: I am a software engineer, no semiconductor expert. But that's the way I understand it.

Andrea ("Powered by POET")

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