Re: New article posted on POET website dated April 4 re 20nm dilemma
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Apr 10, 2014 07:02AM
This is what terafly referenced from the POET site a couple of days ago. I am trying to figure out what it means and why they had it on their site. It was placed there under industry related. It looks like(trying to understand the numbers) that they are telling us that the rest of the semi industry is still miles and years behind POET. But that's just the way I read it. Also, of all the comments on it there's not a mention of POET anywhere. It's like we're a ghost in the real world.
Anyway here it is in it's entirity for any who wish to read and can understand it better than me
Blog
20nm Dilemma Explained
Handel Jones, International Business Strategies Inc.
4/4/2014 06:00 PM EDT 19 comments post a comment NO RATINGS
This article is a follow up to an earlier analysis of the semiconductor roadmap. Fully depleted silicon-on-insulator is the best solution for the 28nm and 20nm technology nodes because of its lower cost and leakage and higher performance than bulk CMOS. The cost of a 100mm2 die in FD SOI at 28nm is 3.0% lower than bulk CMOS and 13.0% at 20nm due to higher parametric yield as well as lower wafer cost. The data also shows that an FD SOI die with comparable complexity to bulk CMOS is 10% to 12% smaller. The combination of the smaller die area and higher parametric yield should give an equivalent product a 20% cost advantage at 20nm for FD SOI compared to bulk CMOS. In addition, at 28nm FD SOI has performance that is 15% higher than 20nm bulk CMOS. (See chart below.) FD SOI can provide energy efficiency levels that are far superior to bulk CMOS for low Vdd and high Vdd. The power efficiency of bit cells is superior for FD SOI because of the lower leakage, along with better alpha particle immunity. Despite these factors, Intel decided to adopt 22nm FinFETs rather than bulk CMOS. It also selected 22nm rather than 20nm in order to eliminate the need for double patterning. Foundry vendors initially planned to migrate to 16/14nm FinFETs rather than 20nm bulk CMOS. But the reality of FinFETs is that the present device structures do not give cost competitive products through Q4/2017. As a result, foundry vendors modified their plans. At TSMC, for example, 20nm bulk CMOS now is projected to represent 10% of total revenues in 2014 ($2.3 billion) and as much as 20% of total revenues in Q4/2014 ($1.1 billion). However, I believe 20nm bulk CMOS will not provide lower cost per gate designs than 28nm, critical for high volume mobile chips. So there is significant uncertainty in the industry regarding the ramp-up rate of 20nm and 16/14nm FinFETs. One possibility is that 28nm wafer volumes will remain high through 2020. (See figure below.) Shrinking FD SOI to 14nm (called 10nm by STMicroelectronics) also will give large cost advantage against FinFETs. Consequently, FD SOI provides both short-term and long-term cost, power consumption, and performance benefits. One reason given for not embracing FD SOI is lack of support in the supply chain and concerns with being nonstandard. However, Soitec, SunEdison, and Shin-Etsu Handotai supply FD SOI wafers. If the industry adopts FD SOI they can expand capacity to address the supply chain challenges. Other issues include the need to develop new libraries and IP, gain expertise in body biasing design capabilities and ensure the establishment of design flows. Leading EDA vendors say these areas can be addressed. Body biasing design techniques are not difficult to learn. When the timeline of the semiconductor industry was based on a two-year window for new generations of process technology, taking an alternate path had high risks. But now with the lengthening of the timeline for new generations of technology -- and with 28nm and variants having high wafer volumes through 2020 -- the higher risk is in not making the optimum decision. I welcome readers' views on how the 20nm dilemma will be resolved. Handel Jones is chief executive of International Business Strategies, Inc. Next page: Wafer, die costs compared PAGE 1 / 2 NEXT >
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Sang kim
Here are some of the important facts on differences of Bulk Si, FDSOI and FinFETs.
Bulk Si successfully ran several technology nodes such as 95, 65, 45, 35 but ends at 28nm. In order to suppress transistor leakage current or drain/source punchthrough a combination of channel doping and retrograde channel implant just below the Si surface were used for Bulk Si. However, such a combination of the channel doping and retrograde implant has a limit as the channel or gate length, Lg decreases to 20nm because precise control of shallower retrograde channel implant just below the Si surface becomes increasingly more difficult, complex and not so effective any more in manufacturing, resulting in high device variabilities or instabilities in transistor electrical transfer characteristics due to high transistor leakage current due to poor process control and manufacturability. That is why Intel adopted 22nm FinFETs.
FDSOI is not the cost issue but transistor device physics issue. FDSOI has two most critical issues: its scalerbility and manufacturability. IBM invented FDSOI technology over a decade ago and created International SOI consortium to develop and manufacture FDSOI but not manufacturable today at any technology node yet. IBM exited FDSOI a long ago.
FDSOI has such a very simple structure consisted of high K metal gate, thin SOI and thick oxide substrate that often make unware of the real issues with FDSOI. The 28nm Bulk is in mass production for several years by major semiconductor companies such as Intel, TSMC, Samsung and others but 28nm FDSOI is not manufacturable today. Even if manufactured today, it would not be competitive with 28nm Bulk because SOI wafe rcost is very much higher than bulk Si wafer.
FDSOI is not scaleable. The beauty of FinFETS over FDSOI is its scaleability. The thin SOI is the key component of FDSOI to suppress transistor leakage current or short channel effects. In order to suppress transistor leakage current for 20nm FDSOI a 5nm thin SOI is required while for 20nm FinFETs the Finwidth at the bottom of Fin that is equivalent to SOI thickness for FDSOI requires 20nm. What a large difference! 20nm for FinFETs vs 5nm for FDSOI for suppressing transistor leakage current or short channel effects. That is why Intel's FinFETs are scaleable to the end of the roadmap, but not FDSOI, not even 14nm FDSOI that requires 3.5nm SOI that is close to the ultimate quantum confinement limit(3nm). That is why Intel 14nm FinFETs will be high volume manufactured in 2015 at the same time when TSMC 16nm FinFETs volume manufacturing starts. Major Semiconductor companies will adopt the FinFETs, not FDSOI. NO RATINGS
@SOI Lady: I am assuming you mean GloFo which said in the past it would support the process.
No doubt there is some busienss being a second source for ST...but as Austin Tech Watcher noted, there seems to be a diminishing set of supporters. NO RATINGS
@Austin Tech Watcher: Thanks for the good perspective, David!
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IBM uses SOI for its Power processors. Your point is valid: Freescale stopped using SOI because of gaps in the design IP, and AMD also retreated. It is hard to gain back the cost of the wafer for $20 chips, I was told.
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"All the industry is going to FinFet, following Intel that has a three years lead and experience"...
Oh sure, I mean Intel has a PERFECT record on process selection, they've NEVER jumped on a technology before it was "ready for prime time" and regretted the consequences, have they? Oh and by the way has anybody seen my bubble memory USB key, I think I must have misplaced it somewhere...hmm!? NO RATINGS
any leaks what the announcement might be @SOI lady?
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And be patient... STMicroelectronics will soon be announcing a "major foundry player" that will be both a dual FD-SOI manufacturing source for ST, plus an open source for the industry. This important piece of news came out of the company's Q4 and FY13 presentation in Paris on January 28th....
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Rick, try the FD-SOI Design Community on LinkedIn for more (not just ST) insight. The FDSOI crowd jumps from 28 to 14nm - not bothering w/20nm --altho Handel is a purist w/respect to nomenclature, it seems ;-) -- anyway, when he says 20nm, the FDSOI folks call it 14nm (that's what they're going head-to-head with, after all). Soitec also has good info - see latest ASN on Gen2FDSOI (28nm performance beats 20nm bulk (and costs 50% less); 14nm matches FinFET (at 20% lower cost). http://www.advancedsubstratenews.com/2014/03/fd-soi-back-to-basics-for-best-cost-energy-efficiency-and-performance/. Also CMP has a been seeing good results in their MPW runs - they've got 140+ users of the 28nm FDSOI PDK (which granted, is provided by ST/Leti) -- hear they're pretty pleased with the results they're seeing.
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In all this lively debate I have not heard of any SOI users beyond STM. Any others out there?
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1. Have detailed data on wafer cost and die cost which support projections shown. The cost data shown was not provided by STM, but independently developed by IBS.
2. FinFETs will ramp into high volume production. The questions are:
The area of concern is for mobile platforms because of the cost challenges. 3. Qualcomm 810 and 808 are very impressive products, and the target for initial devices is H1/2015. Will tie into Mobile World Congress (Barcelona). Is it realistic to expect the next-generation products in FinFETs in H1/2016, or is H1/2017 a more realistic projection? Qualcomm is the volume leader from a foundry perspective along with potentially Apple. 4. Are there other options that are more cost-effective? Fully agree that without a strong supply chain, FD SOI will not become widely adopted. Key question is whether there will be support outside of STM. Any ideas? |
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