I was finally able to sit down and read through the article and I'm amazed that this little morsel has not been highlighted already. I appologize if it has and I missed it, but I think my take-away from this paragraph is new to the board.

From the article:

"In our case, we use substrates made of GaAs. These are

currently available in diameters up to 200 mm, and there is

no fundamental barrier to the production of 300 mm

equivalents. Our preferred growth technique for depositing

III-V layers on this foundation is MBE, and this can be applied to

substrates of this size."

My first impression?....

Let's back up a bit and I'll give you some background.

It had been troubling(not exactly the right word to express my feelings but close enough) me for awhile that they have been working with 3" GaAs wafers and I was pleased when I learned some time ago that they had been also using 6" wafers. Not too surprising as this is R&D, but I was concerned that there was another hurdle to jump of moving to larger wafer sizes on the way to scaling up to commercial production. Not a huge concern but something I filed away in my memory.

I was also concerned that there may be a reason that GaAs wafers were typically smaller than their Si conterparts beyond the obvious different scale of the wafer economies.

With that one paragraph, all my concerns are addressed in a way, that to my knowledge, has not been publicly expressed so far.

1. GaAs wafers are currently available in diameters up to 200 mm. (hence, the goal of production in a 200mm fab)

And...

2. there is no fundamental barrier to the production of 300 mm equivalents.

This little insight may not have been new to some here, but it sure was a great thing to see in print from my point of view.

I've gained a lot more insight on POET from this article. Thank you Dr. Taylor.

Green.