Link: Difference Between SRAM and DRAM

Summary:

1. SRAM (non-volatile) is static while DRAM (volatile) is dynamic

2. SRAM is faster compared to DRAM

3. SRAM consumes less power than DRAM

4. SRAM uses more transistors per bit of memory compared to DRAM

5. SRAM is more expensive than DRAM

6. Cheaper DRAM is used in main memory while SRAM is commonly used in cache memory

Link: Non-volatile Memory

''Unfortunately, most forms of non-volatile memory (SRAM) have limitations that make them unsuitable for use as primary storage. Typically, non-volatile memory either costs more or has a poorer performance than volatile random access memory.''

Link: Poet thyristor memory cell

The configurable nature of the thyristor memory cell 100 as a static memory cell or a non- volatile memory cell has many advantages, including:

- The same footprint of memory cell is used.

- For all high speed functions, the SRAM operation is utilized.

- NV operation is only necessary for a sudden loss of power. Therefore there is no point is sacrificing speed to use NV Ts and O's for all memory operations because the NV operations are somewhat slower than the SRAM's. Instead the NV operation is reserved only for those situations when it is required to protect from power loss.

Clearly this DRAM has significant advantages which are:

- High speed operation, similar to SRAM cell.

- Selective operation of the cell as an SRAM cell or DRAM cell can be controlled by simply disabling the refresh cycle and the store voltage.

- The NV backup mode of operation is available here as well.

- Extremely low power operation is possible.

- Extremely high density as shown by the array layout (same as SRAM, NVRAM)

- No complex sense amps are required. The active of the thyristor device 111 is its own sense amp.

- Not limited by stored charge as in conventional DRAM. The thyristor device is an active device which can supply current instead of charge -active read.

- Finally, the DRAM, SRAM and NVRAM, have a photonic capability as well due to the optical writing and reading function capabilities of the device.

Therefore the kind of operation envisioned is one where the loss of power is monitored by on chip sense circuits. These circuits can operate with ns speeds and can detect power supply changes on microsecond time scales. Therefore the circuits continuously monitor the power supply. If a loss of power is predicted, then before there is a complete voltage drop, the NV writing mechanism kicks in and the state of the memory is captured. Then when power is resumed, the memory state is rewritten back to the SRAM mode and the operation continues. Thus NV operation is utilized only when required and the only overhead penalties are the power failure detect circuits and the NV write circuits.