From the AGM on Rainers blog

https://translate.google.com/translate?depth=1&hl=de&rurl=translate.google.com&sl=de&tl=en&u=http://rainerklute.wordpress.com/2014/08/16/poet-hauptversammlung-bestaetigt-positiven-ausblick/

From Rainer:

''What is united with the prototype chip that is all POET components themselves?

Geoffrey Taylor: Yes, the masks for that we have completed last week.''

If he was talking about the masks of the 100nm milestone they would have already been completed prior to a week before the AGM. If Dr. Taylor said something along these lines I think its possible that the 40nm reduction could already be complete. Why would we be kept in the dark, NDA. If the 40nm masks are complete I would think it would be safe to say revenues in a very small amount of time.

What is a mask?

All semiconductor devices are manufactured as a series of layers on some substrate material (normally silicon dioxide). The exact specifics can vary considerably, but at a high level of abstraction you can think of a semiconductor as a series of very thin, stacked layers. Each layer is created from a different mask, and different layers can be made of different materials. Transistors are normally created by stacking the poly and active layers in a particular way. Capacitors can be created by stacking two different metal layers, or a variety of other ways.

The masks used to create each layer are basically like a 1-bit bitmap: they have a grid of squares (similar to pixels) that are either "on" or "off". And this is where process size comes into play. The process size defines lambda, which is how large each of those squares will be on the chip.

http://www.10stripe.com/articles/what-does-process-size-mean.php