Aiming to become the global leader in chip-scale photonic solutions by deploying Optical Interposer technology to enable the seamless integration of electronics and photonics for a broad range of vertical market applications

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Message: Re: Softening?
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Sep 03, 2014 06:16PM
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Sep 03, 2014 06:31PM

They have definitely backed off on previous bullish performance metrics of the 100nm (see below). They went from 50x to 20X faster and lower power by 4-10 times to "could be equivalent to 3-4 nodes ahead of mainstream technologies" This is slightly confusing. If this is the case 100nm would be equivalent to 3-4 nodes smaller compared to silicon. Silicon went 130nm- 90 - 65 - 45 - 32 - 22 - 14nm?? - 10nm??. So is our PET 100nm equals to somewhere between 45nm/ 32nm in silicon. 40nm in Pet should match up with 14nm/ 10nm in silicon??

Definitely a change in performance communicated in NRs. It appears, based on the latest NR, 40nm is need to beat the smallest silicon node at this point. I am slightly unsure of this because I always thought we could blow silicon out of the water simply because of our high electon mobility when compared to silicon. Keep in mind I am no semconductor expert. I will send an e-mail to Chris Chu asking for an explaination.

Whatever the case may be our technology is needed and PET is just a stepping stone to POET (full optical integration) and ultimately quantum computing/ single electron transistors.

Sept. 2, 2014

The PET PDK and process offers lower cost and simpler process fab options for applications that do not require the full POET optical feature set. Due to the high mobility inherent in III-V materials, PET technology is predicted to deliver performance, which could be equivalent to 3 to 4 nodes ahead of mainstream technologies.

Mar. 4th, 2014

The 100-nm goal is matched to the state-of-the-art commercial III-V foundry capabilities and will demonstrate greater than 20x speed improvement together with lower power consumption by 4x to 10x, depending on the application, compared to silicon at smaller nodes.

Jan. 6th, 2014

The 100-nm goal is matched to the state-of-the-art commercial III-V foundry capabilities and will demonstrate the greater than 50x speed improvement together with lower power consumption by a factor ranging from 4 to 10 depending on the application as compared to silicon at smaller nodes.

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Sep 04, 2014 07:05AM
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