Thanks for this link to the Chip Design article, LookinGIntoIt!

Very informative read, especially for analog design! The article helps to gain a better understanding of chip design and explains why developing a PDK is an essential, but also complex and time-consuming process. The article makes plain why a collaboration between process and PDK developer (POET Technologies) and PDK tool developer (Synopsys) is essential.

"There are so many hurdles to overcome when developing a PDK. The current lack of standards forces PDK providers to develop their own implementation methodologies, while at the same time satisfying customer desires and adapting to continuously evolving EDA tools. Finding a balance between fulfilling individual customer expectations and meeting time-to-market requirements is the biggest challenge in PDK development today."

Regrettably the Chip Design article does not come with a publication date, but it seems to be from 2003, 2004, or so. Today standardization is much better, as described in "Interoperable Process Design Kits (iPDKs) Gain Momentum" from 2011 on the Synopsys website. However, not each and every aspect is standardized yet, therefore carefully selecting the EPA tool provider is still essential.

In this context it is especially interesting that Synopsys and GlobalFoundries have developed and released interoperable process design kits (iPDK) for GlobalFoundries' processes, see this news release (hint, hint)!

Even if standardization is better today, more challenges remain according to the Chip Design article:

"Add to those concerns, the pressure of meeting customer needs in a timely manner and it’s easy to see that a speedy PDK release often forces a compromise between conflicting requirements."

The authors of the Chip Design suggest to decrease the number of features in the PDK, and provide DRC and models only as an initial offering. This is why POET Technologies restricts their initial PDK offering to POET's electrical features (PET).