Is the information in this comment, as revealed by R Colin Johnson, public knowledge through a POET News Release? It may been, I just don't recall. Anyone verify this?
Re: Is GaAs using silicon manufacturing infrastructure?
R_Colin_Johnson 9/15/2014 5:11:24 PM
POET is mum on the details, but claims to be capable of 8" wafers, and says there is a company they signed NDA with which can fab 4 - 8 inch wafers in the same chamber. However, most others making III-V transistor channels are trying to put them on Si wafer with special buffer layers to handle the lattice mismatch.
http://www.eetimes.com/document.asp?doc_id=1323892&#msgs