Aiming to become the global leader in chip-scale photonic solutions by deploying Optical Interposer technology to enable the seamless integration of electronics and photonics for a broad range of vertical market applications
Message: Nice long reply on EE Times from POET
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@Scott Elder: Wall at 4GHz?
Scott, I asked POET what they thought about your long comment and got an even longer answer:
POET Technology is revolutionary in that it is the first – and to our knowledge, only – technology to integrate electrical devices used in large scale ICs today in native III-V. For high speed digital logic, they are both pHFET and nHFET (enabling static CMOS digital circuit topology), both pHBT and nHBT for analog and mixed signal circuits and an optical thyristor to fabricate optical devices. The structures are compatible with scaling to nanometer scale by leveraging processes and lithography capabilities already proven in Si CMOS. We are expecting a minimum of 5X higher mobility of carriers in these devices when compared to native Si devices. The technology is also capable of integrating optical and electro-optical devices which bring optical signaling and signal processing to the same component.
To address some of the readers' comments regarding performance, density and cost:
- For high speed digital logic implemented using the nHFET and pHFET transistors. Comparing POET to Silicon CMOS for digital SoCs, logic performance will be 4 nodes better in power AND 3 nodes better in speed. We expect comparable if not better density as we expect to require far less buffering and upsizing of logic cells.
- For analog and mixed signal circuits. In addition to p and n HFET's higher transconductance, lower noise figure and larger linear operating range, we also have nHBT and pHBT devices with effectively zero minority carrier storage, very high gains and very fast transit times. Mixed signal performance will be better due to lower on chip switching noise, and better digital to analog isolation due to the semi insulating substrate, and the circuits in general will be smaller due to higher drive per unit size. We expect to support serial I/O at 50Gbps if not 100Gbps.
- Lastly are the optical capabilities of the POET process where our customers will have the ability to have optical I/Os on their devices along with digital and/or analog circuitry described above. We expect on chip memory to be denser and faster due to thyristor based 2-element memory cell and much better sense amplifiers.
All of the capabilities described above will allow designers of complex systems and SoC solutions to innovate in ways that have not been possible to date with existing processes. These system integration possibilities will enable lower solutions and manufacturing costs.
Looking at IC costs, one needs to consider the total cost of ownership viewpoint in making comparisons. If you look at cost/sq mm of state of the art CMOS, these numbers generally assume high fab utilization and do not amortize the cost of R&D, including NREs. The number of companies that can develop the process and manufacturing capability for state of the art CMOS can now be counted on one hand, and that is because there are only a handful of customers or vertically integrated companies that have applications where the volumes can absorb the development costs and fill the fabs. With respect to 40nm and manufacturing technology, our FEOL process is substantially simpler than an equivalent CMOS technology, and our BEOL is the same. With adoption and resultant volume scaling, we expect that the wafer costs will come down thanks to volume and manufacturing is within the capability of 4 to 6 year old toolsets. NRE costs will be significantly lower as compared to like performance silicon nodes, drastically lowering the breakeven point on a unit basis. Users of this technology will address applications that differentiate on performance capabilities or differentiate on cost due to system level partitioning and optical integration not even possible with existing technologies, and will be able to command differentiated product pricing. Bottom line is that a whole new set of business cases become possible with this technology that were previously impossible due to inaccessibility of required performance.
In summary, POET technology will not replace, but supplement CMOS in applications requiring the highest performance, integration and/or lowest power. Our vision is that many foundries will eventually offer POET Technologies processes along side of their existing processes to their existing customer base to enable solutions that are not realizable today with any other process out there.
Scott, I asked POET what they thought about your long comment and got an even longer answer:
POET Technology is revolutionary in that it is the first – and to our knowledge, only – technology to integrate electrical devices used in large scale ICs today in native III-V. For high speed digital logic, they are both pHFET and nHFET (enabling static CMOS digital circuit topology), both pHBT and nHBT for analog and mixed signal circuits and an optical thyristor to fabricate optical devices. The structures are compatible with scaling to nanometer scale by leveraging processes and lithography capabilities already proven in Si CMOS. We are expecting a minimum of 5X higher mobility of carriers in these devices when compared to native Si devices. The technology is also capable of integrating optical and electro-optical devices which bring optical signaling and signal processing to the same component.
To address some of the readers' comments regarding performance, density and cost:
- For high speed digital logic implemented using the nHFET and pHFET transistors. Comparing POET to Silicon CMOS for digital SoCs, logic performance will be 4 nodes better in power AND 3 nodes better in speed. We expect comparable if not better density as we expect to require far less buffering and upsizing of logic cells.
- For analog and mixed signal circuits. In addition to p and n HFET's higher transconductance, lower noise figure and larger linear operating range, we also have nHBT and pHBT devices with effectively zero minority carrier storage, very high gains and very fast transit times. Mixed signal performance will be better due to lower on chip switching noise, and better digital to analog isolation due to the semi insulating substrate, and the circuits in general will be smaller due to higher drive per unit size. We expect to support serial I/O at 50Gbps if not 100Gbps.
- Lastly are the optical capabilities of the POET process where our customers will have the ability to have optical I/Os on their devices along with digital and/or analog circuitry described above. We expect on chip memory to be denser and faster due to thyristor based 2-element memory cell and much better sense amplifiers.
All of the capabilities described above will allow designers of complex systems and SoC solutions to innovate in ways that have not been possible to date with existing processes. These system integration possibilities will enable lower solutions and manufacturing costs.
Looking at IC costs, one needs to consider the total cost of ownership viewpoint in making comparisons. If you look at cost/sq mm of state of the art CMOS, these numbers generally assume high fab utilization and do not amortize the cost of R&D, including NREs. The number of companies that can develop the process and manufacturing capability for state of the art CMOS can now be counted on one hand, and that is because there are only a handful of customers or vertically integrated companies that have applications where the volumes can absorb the development costs and fill the fabs. With respect to 40nm and manufacturing technology, our FEOL process is substantially simpler than an equivalent CMOS technology, and our BEOL is the same. With adoption and resultant volume scaling, we expect that the wafer costs will come down thanks to volume and manufacturing is within the capability of 4 to 6 year old toolsets. NRE costs will be significantly lower as compared to like performance silicon nodes, drastically lowering the breakeven point on a unit basis. Users of this technology will address applications that differentiate on performance capabilities or differentiate on cost due to system level partitioning and optical integration not even possible with existing technologies, and will be able to command differentiated product pricing. Bottom line is that a whole new set of business cases become possible with this technology that were previously impossible due to inaccessibility of required performance.
In summary, POET technology will not replace, but supplement CMOS in applications requiring the highest performance, integration and/or lowest power. Our vision is that many foundries will eventually offer POET Technologies processes along side of their existing processes to their existing customer base to enable solutions that are not realizable today with any other process out there.
"
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