POET Technologies holds a patent on a "Thyristor Memory Cell Integrated Circuit".

A memory cell can store a bit of information in a phase-change material (chalcogenide glass, according to the patent text). "Phase-change" means that the material can be switched between a crystalline and a non-crystalline state ("phase") with a high electrical resistance in one phase and a low resistance in the other, representing a "0" resp. "1" non-volatile bit.

The memory cell in parallel also stores a volatile bit. This bit resides in the thyristor circuitry and offers a much faster access. You can use a memory cell array one or the other configuration, depending on what you need more: speed or permanence. Or something in between by copying the volatile state to the non-volatile state from time to time.

POET Technologies has a memory implementation on its 2015 agenda, see page 21 of the corporate presentation:

SRAM Structure

Develop and successful demonstration of 2T thyristor-­based bit cell, read and write amps. Goal of layout density greater than equivalent CMOS bit cell at same node.

SRAM is the fastest and most expensive type of memory. In CMOS, it is usually made of 6 transistors per memory cell. POET's memory cell is made of only 2 thyristors, so the goal of a density greater than equivalent CMOS bit cell at same node [size] seems achievable, provided that transistors and thyristors are roughly of the same size. Permanence is not an issue with SRAM, but I assume they'll build the memory as outlined in the patent.