Aiming to become the global leader in chip-scale photonic solutions by deploying Optical Interposer technology to enable the seamless integration of electronics and photonics for a broad range of vertical market applications

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Message: Sedar
The Company has: 1. Successfully produced numerous distinct devices under the POET process, including on-chip continuous-wave lasers and switching lasers with the potential for eliminating chip-to-chip metallic interconnects, complementary hetero-structure field effect transistors (HFETs), optical thyristors, pulsed lasers, super-radiant light emitting devices, and infrared sensors with potential usage for multi-spectral and uncooled operation – all able to be monolithically fabricated through the POET process. 2. Established Technology Design Kits (“TDK”) documentation. TDKs comprise a library of comprehensive design rules and device parameters for the POET technology that will eventually enable customers and partners to implement the POET fabrication process into their preferred foundries. 3. Actively engaged BAE Systems Inc. (“BAE Systems”) to replicate the POET process with greater precision and larger scale using advanced ebeam writing tools. This contractual effort with BAE Syatems will accelerate the “Lab-to-Fab” transition of the POET technology to a manufacturing status of 6" wafer scale. The target of the effort is 40-nm dimensions for the critical features. This engagement is meant to support the development and verification of the foundation devices and design enablement kits. Additionally, it will provide the baseline FEOL (Front End Of Line) process flow in a manufacturing environment and toolset. 4. Continued the development of the 40-nm Planar Electronic Technology (“PET”) Process Design Kits (“PDKs”). PTI is utilizing Synopsys’ TCAD tools and services to develop the PET and POET PDKs. PDKs are used by 3rd party chip developers to create IP libraries that would be used to implement System on Chip (“SoC”) integrated circuits. Availability of the PDKs will enable early evaluation of the performance advantages of POET technology and design of IP required for SoC implementation.
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