Intel: Understanding Multiple Patterning At 14 Nanometers And Below

Multiple patterning is an advanced lithographic technique now being used by Intel (NASDAQ:INTC) and others in leading edge semiconductor manufacturing. As is well known, semiconductor manufacturers pursue roughly 2x shrinks in transistor size every two years to reduce wafer printing costs as well as achieve product performance improvements. It is extremely important to understand these manufacturing processes, which can cost roughly $10 billion in capital expenses each year.

It is multiple patterning which is the crucial enabler of the current, latest generation semiconductor nodes. Intel's 14 nm process makes use of self-aligned double patterning (SADP), and their 22 nm process also likely made limited use of it. TSMC's (NYSE:TSM) latest upcoming generation process, called 16 FF+ (FinFet), and Samsung (OTC:SSNLF) and GlobalFoundries' latest process, 14 nm, can all be believed to use multiple patterning.

In order to understand Intel's latest generation products (Broadwell, Core M, and the upcoming Broxton), we need to understand what multiple patterning means and how it works. Similarly, all of Intel's competitors products, such as Qualcomm (NASDAQ:QCOM) and Apple (NASDAQ:AAPL), based on ARM (NASDAQ:ARMH) architecture, will have to make use of it at nodes of 16 nm and beyond. Furthermore, the higher costs of multiple patterning imply that semiconductor designers are likely to start altering their designs in order to compensate for it. In Intel's case, its designers have adjusted to multiple patterning already, and its designs are well positioned for future success.

Each competitor will implement multiple patterning in a different way and it will pose a key added source of process complexity and competitive differentiation. This article will provide a basis for understanding multiple patterning.

Printing at sub-optical resolution

In essence, multiple patterning refers to a range of procedures for printing lithographic features at smaller sizes than the optical resolution of the printing system. That resolution is limited due to the diffraction properties of light, as discussed in a lecture by Intel's Sam Sivakumar. Wikipedia has some good pictures of multiple patterning, but I will focus on verbal descriptions here. Although multiple patterning provides an eventual cost reduction due to end-product improvement, it increases the cost of wafer processing.

There are two types of multiple patterning that get discussed most frequently. In the first type, called double exposure or litho-etch-litho-etch, a wafer is sent through the lithographic scanner twice, with a different mask each time. On the first pass, the maximum possible resolution is achieved due to the diffraction limit. This leaves you with printed features of some minimum width, call it w, with spaces around them of width L.

The printed space w can be much finer than the "empty" space L, say L = 3w, due to engineering of the photoresist to have a controlled sensitivity to light. On the second pass, the new pattern to be printed, again at minimum feature width w, is shifted slightly with respect to the first, so that it falls in the unprinted gaps (the L space). In this way you wind up with two sets of features of length w instead of just one. You have effectively cheated the optical resolution limit of the system to print features that are twice as fine as the printer allows by itself.

Note that without advanced photoresist or other technology to enable tight feature spacing, w < L, this technique would not work. The technique also obviously requires excellent overlay precision on the wafer scanner in order to precisely control the offset between different exposure steps.

The second type of multiple patterning techniques are called self-aligned techniques, pitch splitting, as termed by Intel, or the sidewall image transfer approach, as termed by IBM (NYSE:IBM). This is a clever technique that makes use of a very directional etch, or an etch which only goes a specific vertical depth. In self-aligned double patterning (SADP), the minimum feature width can be doubled, and there are analogous techniques for quadruple and even octuple patterning. In pitch splitting techniques, only a single pass through the lithography machine is required. However, the technique is primarily geared toward printing of basic 1-D patterns like lines.

Since the lithography steps, consisting in passes through an ASML (NASDAQ:ASML), Nikon, or other scanner, are known to be the most expensive part of the wafer fabrication process, multiple exposure patterning costs more than self-aligned patterning. However, both processes require more etching, photoresist, and other processing steps than would be required for plain single exposure. Thus, multiple patterning incurs a higher expense.

Current applications

Before discussing current applications of multiple patterning, let's review available data on the current timelines of production technology for the semiconductor manufacturers. As stated in TSMC's latest earnings release, TSMC is ramping its 16 nm process in the third quarter of this year 2015. Intel has some lead time on TSMC, and has been selling its 14 nm products since fourth quarter 2014. They are now available for example in Core M branded products, such as in the new Apple Macbook, recently reviewed at AnandTech.

On its last earnings call, Intel stated that it would begin ramping its 10 nm process in the third and fourth quarter of this year. TSMC plans to ramp 10 nm in the fourth quarter of 2016 and expects revenue contribution in early 2017. It's hard to say when these ramps will translate into products available on the broader market, but a rough guideline suggests 2H 2016 for Intel 10 nm and 2H 2017 for the rest of the industry 10 nm.

10 nanometer production will require extensive use of multiple patterning techniques. At a recent IEEE Design & Test Round Table discussion, panelists concurred that regular lithography is diffraction limited at around 80 nm pitch, where pitch refers to the width of a feature. This explains why SADP was a necessity for Intel's 14 nm process, which was reported to have pitches as short as 42 nm.

In 2014, Intel released the specifications for its 14 nm node technology compared to 22 nm, which I reproduce in the chart above. This allows us to estimate pitch lengths at 10 nm. The lowest of these estimates is 30 nm for the transistor fin pitch. However, SADP should only be able to (at most) half the 80 nm optical resolution of the system, and this will be further limited due to overlay precision of the scanner. Thus, SADP is limited to probably 45-50 nm maximum resolution. This means that self-aligned quadruple patterning (SAQP) or even more advanced techniques will be necessary at 10 nm.

The fact that even the 22 nm process had a 60 nm fin pitch suggests that SADP was used in 22 nm as well. However, the interconnect pitch could have remained on single patterning.

At 10 nm, both the first metal (interconnect) layer and fin layer are likely to require SAQP, whereas the transistor gate layer may only require SADP. Note that these estimates are specifically based on Intel's numbers, and may vary for TSMC, Samsung and GlobalFoundries.

Implications for industry trends

Given that multiple patterning must be employed to shrink to the next node, it is necessary to decide which kind of multiple patterning to employ. For a complex 2-D shaped circuit, multiple exposure patterning is necessary, since self aligned patterning is best suited for lines and repetitive structures. However, the requirement of multiple exposures makes the manufacturing process more expensive. Thus the circuit designer can essentially choose to either make a simpler, 1-D layout circuit, which is cheaper to fabricate, or to make a more complicated 2-D layout which is more expensive.

As Sivakumar talks about in his lecture, Intel's approach to this multiple patterning cost problem was to go to 1-D layouts. Evidently, the circuit designers were at the mercy of the process designers. On the transition from 65 nm to 45 nm, they simplified the logic layout into structures that looked like regularly spaced lines with cuts in them (see image here), and they have retained this pattern since then. The step of forming the lines can be done with pitch splitting, or single exposure lithography. The step of forming the cuts in the lines still generally requires multiple exposure, but this is at least restricted to the simpler pattern of cuts.

To recap, Intel simplified its logic circuitry into a 1-D layout on each layer. Ultimately, the circuits still require 2-D connections, at least on the interconnect layers, but, unless I am otherwise mistaken, these 2-D connections can be formed by simply stacking up 1-D connections with appropriately positioned vertical contacts.

Intel has the advantage that it controls all its own design and manufacturing in the same house. It was thus able to make this educated design decision presumably much sooner than the other circuit designers who were less closely informed of (controlled by) the costs of manufacturing their designs. In the case of the foundries, such as TSMC, there has been no need to impose on customers the demand for 2-D or 1-D layouts in the past, since the customer could simply pay more for working in 2-D.

With the environment of highly increasing process complexity, going into SAQP at 10 nm, it seems likely that industry logic design will all follow Intel's route into the simplest possible options - 1-D circuit layout design. We can speculate that this might have a significant effect on customers for TSMC and the other foundries, such as ARM, Apple, and Qualcomm. This will not be a sudden change, as they will have seen it coming over time, but it may nevertheless prove significant that they are increasingly forced to switch from 2-D to 1-D layouts.

What seems most likely is that the increase in manufacturing complexity will tend to have a homogenizing effect on circuit layout and design. Circuit designers' layouts will all start looking like 1-D SADP layouts. Thus, differences in architecture, for example, will become increasingly marginalized compared to differences in process size. This is essentially positive news for Intel, at least in the short term, since its process has a small but documented lead on its competitors.

Conclusion

I expect multiple patterning is a term we will continue to hear increasingly frequently within the semiconductor world. As it stands, it has still not been widely discussed outside of technical and academic circles, and yet it underlies all future product generations and capabilities. It has started popping up more on earnings releases for companies like Intel, TSMC and ASML, and we should pay attention to what this term means.

Multiple patterning is currently being applied at all the leading edge nodes, and will take another large step forward at the next node (10 nm) in 2016-2017. SAQP will be a must for 10 nm, and the cut mask process will likely involve double or even triple exposure multiple patterning.

Advances in multiple patterning complexity are likely to drive significant layout simplification over the next few years. Since Intel has already incorporated these changes, it is well positioned for future success. In contrast, Intel's competitors are likely to need to increasingly adopt simplified 1-D logic layouts. Due to increased process complexity, there will likely be even more differentiation between process nodes for Intel and TSMC, but probably less differentiation between process designs.

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