Disco, "Semiconductors from Idea to Product" is a great read (although long), thanks for sharing. I found a few things very interesting.

1) This should be front and center "The length of the wires is the biggest factor in figuring out the delay of the clock travelling along them, and it’s that delay that’s the main limit for the peak operating frequency of a given block."

Imagine not having to use wires and to be able to use something such as optical interconnects (mmmm, I wonder who can do that). Not to forget the other issues with heat, etc.

My real take home message is that this whole process is extremely complex, so I am sure glad that POET has the new staff with the many years of technical experience, not to mention the relationship with Synopsys. I also think this highlights how significant it is that POET can be easily integrated into current semiconductor production facilities, supports existing manufacturing and testing infrastructure, supports existing silicon CMOS post fabrication procedures, and is compatible with existing and planned package technology.

2) Not sure what the author meant exactly, but I like this comment (bold is mine) "No, we’re going to talk about things a little bit further down, at the level of the silicon (but not for long!) chips that do all the computing in modern devices, be they smartphones or otherwise."

3) Similarly, I like (bold is mine) "Silicon dice, and I presume it’ll be the same with the replacement materials for silicon when they eventually arrive, have their circuits etched into them by a combination of lithography and chemical processes"

PS. Anyone else still wondering what the relationship with Synopsys is all about (we don't seem to be paying them)? I can't imagine what they do comes cheap.