With foundries close to qualifying eFlash at 40nm, the 40nm node will soon become the preferred node for chips targeting Internet of Things (IoT) applications. Processes such as TSMC’s 40ULP technology offer expanded threshold voltages (VT), long channel lengths and innovative circuits like multi-bit flip flops to reduce power.

This webinar will provide details on how foundation IP—logic libraries and embedded memories--can help designers of IoT applications take advantage of the power benefits available in 40nm process technologies. It will describe:

• Why the 40nm process is gaining traction in IoT applications
• How memory compliers can leverage assist circuitry to support the lowest operating voltages
• How ultra-low leakage libraries can be used to build always-on logic blocks, reducing leakage by up to 100X
• How always-on logic blocks can connect directly to a wide variety of energy sources while bypassing voltage regulators

SPEAKER

Ken Brock

Product Marketing Manager, Logic Libraries

Synopsys

https://webinar.techonline.com/20022?keycode=CAA1CC&cmp=WEBR-dwip100448-HPE

Maybe that's why "they" wanted POET to go down to 40nm

The Company recently reported a contractual effort with a “3rd party foundry” to accelerate the transition from “Lab-to-Fab” of the POET technology to a manufacturing status at the 6” wafer scale. The target of the effort is 40-nm dimensions for the critical features.

http://www.poet-technologies.com/poet-technologies-announces-an-update-on-the-lab-to-fab-transition-and-the-100-nm-and-40-nm-scaling-program/

cheers