I have to say, Suresh Vankatesan does seem to have an exemplary work ethic, presumably he's also very knowledgable of current & future semiconductor needs.
All Patents: http://patents.justia.com/inventor/suresh-venkatesan
Here's his latest patent focusing on 14nm:
MIDDLE-OF-THE-LINE CONSTRUCTS USING DIFFUSION CONTACT STRUCTURES
Application number: 20150187702
Type: Application
Filed: Mar 12, 2015
Issued: Jul 02, 2015
Inventors: Mahbub RASHED (Santa Clara, CA), Yuansheng MA (Santa Clara, CA), Irene LIN (Los Altos Hills, CA), Jason STEPHENS(Beacon, NY), Yunfei DENG (Sunnyvale, CA), Lei YUAN (Sunnyvale, CA), Jongwook KYE (Pleasanton, CA), Rod AUGUR (Hopewell Junction, NY), Shibly AHMED (San Jose, CA), Subramani KENGERI (San Jose, CA), Suresh VENKATESAN (Los Gatos, CA)
Application Serial: 14/645,598
TECHNICAL FIELD
The present disclosure relates to middle-of-the-line (MOL) constructs. The present disclosure is particularly applicable to MOL constructs for 14 nanometer (nm) technology nodes and beyond.
BACKGROUND
As technology advances, the importance of logic scaling continues to grow. However, traditional approaches to logic scaling are no longer effective due to lithographic limitations. In recent years, double and triple patterning techniques have been implemented for metal1 layer structures to mitigate the effects of such limitations by enabling metal1 layer structures to be formed closer to each other. However, the use of additional patterning processes also have their limits with respect to logic scaling as a result of increased complexities, high costs, and reliability issues that may be associated with further patterning (e.g., quadruple patterning) of these metal1 layer structures.
A need therefore exists for other logic-scaling-related constructs that do not rely on further patterning of metal1 layer structures, and enabling methodology.
