"* for anyone who's interested, I'll put on my EE hat for a bit.

amongst other things, input gate node capacitance is crucial to the performance of high bit-rate receivers, i.e., capacitances of the FET gate, the pin, and any strays from bond wires and pads. when things are monolithically integrated as with P[O]ET, the bond pads and wires are no longer present, so strays are greatly reduced. then, further improvents are obtained by reducing pin capacitance and FET gate width. result: higher speed and/or better sensitivity."

Rob, if pushed, I'd have to say I pretty much can't dispute what you said above.