When the term IP first came into popular usage for IC design, it was primarily conceived as blocks of design content that were bought occasionally from external sources. A customer might use one or two in a design, and expect one delivery with perhaps some minor updates before tapeout. Over the last 18 years, this notion has changed quite a bit as design complexity has increased and the level of integration required for SOC development has risen dramatically.

What have we learned in the intervening years? For one thing, IP is frequently developed internally as well as externally. So, IP management and release systems are not just for so-called IP providers anymore. Furthermore, the necessities of design reuse have formalized a lot of the processes regarding sharing of design blocks internally. It’s easy to think of it still being a matter of just freezing a design block and handing it off as being a workable method of releasing IP. However, this is far from the case.

https://www.semiwiki.com/forum/content/5122-why-your-ip-release-methodology-can-make-break-reuse-success.html

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The countdown to the end of Moore's Law is coinciding with the rising complexity in system-on-chip (SoC) designs. And that's not a mere coincidence. The leverage that has long been coming from shrinking process nodes in terms of cost, performance and power benefits is now increasingly being accomplished through greater efficiency in SoC designs.

Take, for instance, interconnect, one of the few configurable venues left on the SoC real-estate. So far, internal chip design teams have been relying on legacy interconnect technologies such as hierarchical bus and configurable crossbar. However, cost imperatives, time-to-market pressure, and design challenges like routing congestion and place-and-route issues are forcing SoC designers to consider the interconnect IP implementations.

Montage Technology, a chip supplier for home entertainment and cloud computing markets, has licensed Arteris FlexNoC IP for its digital set-top box (STB) chipsets. Arteris' network-on-chip (NoC) technology alleviates bottlenecks in moving large blocks of data by packetizing data and serializing transmission over fewer wires than required in other interconnect technologies.

https://www.semiwiki.com/forum/content/5118-interconnect-watch-3-chip-design-merits-network-applications.html

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A new powerhouse to dominate over AMAT
Combination of best of Breeds
KLAC shareholders get $32 cash plus stock

The wedding invitation.......
Lam Research Corporation (NASDAQ: LRCX) ("Lam") and KLA-Tencor Corporation (NASDAQ: KLAC) ("KLA-Tencor") today announced that they have entered into a definitive agreement, unanimously approved by the boards of directors of both companies, for Lam Research to acquire all outstanding KLA-Tencor shares in a cash and stock transaction.

KLA-Tencor stockholders will be entitled to elect to receive for the shares of KLA-Tencor stock they hold the economic equivalent of $32.00 in cash and 0.5 of a share of Lam Research common stock, in all-cash, all-stock, or mixed consideration, subject to proration as more fully described in the merger agreement. The transaction values KLA-Tencor at approximately $67.02 per share, or $10.6 billion in equity value based on the closing stock price of Lam on October 20, 2015.

This combination will create unmatched capability in process and process control, delivering optimized results in partnership with its customers by reducing variability and accelerating yield, ultimately helping the semiconductor industry extend Moore's Law and performance scaling generally.
The combined company will have approximately $8.7 billion in pro forma annual revenue

https://www.semiwiki.com/forum/content/5121-best-possible-merger-semiconductor-capital-equipment-business-history.html