Nice digging!!

I remember posting about this in 2014, the mysterious "3rd Party Foundry"..

Could UMC have been it the whole time? Seems plausible.

At the time we were thinking GF with the Ajit connection, or BAE but it didn't make sense as they named BAE many times previously.

More plausible than GF anyway, IMO..

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"POET reported that it is encouraged by the promising initial results of its wafers sourced from its epitaxial wafer partners processed in the Wavetek facility using POET’s proprietary technology, which has recently been transferred under a Nondisclosure Agreement between POET and Wavetek. The Agreement addresses all current manufacturing requirements (including Vertical Cavity Surface Emitting Lasers (VCSELs)) in POET’s ongoing commercialization initiative. A previously announced subsisting manufacturing services agreement was limited to prototype demonstration of VCSELs."

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This almost revives the whole 40nm side of things as well.. Very curious.

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Let's entertain this idea and review shall we?

(WARNING:By reading this, some people on this forum might learn something and that in turn could distract one from constantly complaining/talking about the share price of an investment the majority barely understand)

Mention of 3rd Party Foundry in chronological order:

POET Technologies Announces a Collaboration with Third Party Foundry to Reproduce and Enhance Repeatability of the 100-nm Results and Shrink its Planar Electrical Technology Process (PET) to 40-nm Scale

September 2nd, 2014

Toronto, ON, and Storrs, CT,September 2nd, 2014 – POET Technologies Inc. (TSX-V: PTK; OTCQX: POETF) (“the Company”) – developer of the planar opto-electronic technology (POET) platform for monolithic fabrication of integrated circuit devices containing both electronic and optical elements on a single semiconductor wafer – today announced an agreement with a “3rd party foundry” to reproduce and enhance repeatability of the 100-nm scale results obtained at the Company’s labs (the “POET labs”) located at the University of Connecticut (UCONN). The “3rd party foundry” will also assist the POET team in shrinking the 100-nm PET devices and process to a 40-nm feature size.

Having developed a structure suitable for scaling POET transistors to the 100nm scale, POET has actively engaged a third party foundry to replicate the POET results with greater precision and larger scale using advanced ebeam writing tools. Definition and repeatability of 100-nm has been difficult in the POET labs due to the limitations of available lithography tools and other equipment. The collaboration gives the POET team access to superior capability and diagnostics, allowing the POET approach to start to scale to both 3″ and 6″ wafers with much larger device count and across wafer alignment. The fine features will then be merged with optical lithography and other procedures necessary to transition to a manufacturing environment. In addition, the effort will target line width reductions from 100-nm down to 40-nm which should enable POET performance parameters to compete with present state-of-the-art processes. The reduction will be parallel to our efforts with our Synopsys TCAD collaboration.

Dr. Geoff Taylor, Chief Scientist and Board member noted: “Developing the 100-nm feature size technology in the current POET labs has proven to be challenging. With the collaboration of our “3rd party foundry”, we now have access to state of the art equipment highlighted by a state of the art ebeam writing tool. This will help us make the process more stable and predictable and help prove our process in a true manufacturing environment.”

This announcement follows another announcement today from the Company regarding collaboration with Synopsys and the creation of the Company’s first Process Design Kit (PDK). This collaboration will see the development of an advanced model of the Company’s PET devices targeting a technology node of 40-nm, a significant production node of highly integrated systems-on-chip (SoC) silicon CMOS device. The results of the physical devices at 40-nm developed at the “3rd party foundry” can then be correlated to the models of the PET technology developed using TCAD tools from Synopsys and vice-versa.

Mr. Peter Copetti, Executive Chairman Interim CEO concluded: “We now believe we have the right collaboration in place with Synopsys and our “3rd party foundry” to model our technology down to 40-nm and correlate our process to real physical device measurements. This should provide us with results needed to showcase our technology to potential customers at the optimum node for our platform. We expect synergistic benefits from having parallel operations with the same end target.”

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POET Technologies Announces an Update on the “Lab-to-Fab” Transition And the 100-nm and 40-nm Scaling Program

October 22nd, 2014

Toronto, ON, and Storrs, CT, October 22, 2014 – POET Technologies Inc. (TSX-V: PTK and OTCQX: POETF) (the “Company”) – developer of the planar opto-electronic technology (“POET”) platform for monolithic fabrication of integrated circuit devices containing both electronic and optical elements on a single semiconductor wafer – today announced several key updates on its “Lab-to-Fab” transition and its 100-nm and 40-nm scaling program and several operational updates.

“Lab-to-Fab” Transition: 100-nm and 40-nm Scaling Program Update

The Company recently reported a contractual effort with a “3rd party foundry” to accelerate the transition from “Lab-to-Fab” of the POET technology to a manufacturing status at the 6” wafer scale. The target of the effort is 40-nm dimensions for the critical features. This engagement will support and enhance the development and verification of the foundation devices and design enablement kits. Additionally it will provide the baseline FEOL (Front End Of Line) process flow in a manufacturing environment and toolset. Fabrication at 40-nm (Silicon CMOS) is a mature semiconductor process that has been in existence since 2007-2008. This enables POET to target a mature process flow and revitalize existing manufacturing lines while delivering predicted performance and power efficiencies that rival today’s state of the art process node in the sub 20-nm range (Silicon CMOS). This effort will enable and progress two of our current key initiatives which the Company is currently working on, a 100-nm ring oscillator which is a common demonstration vehicle for performance and an integrated 50GHz VCSEL device, both targeted for Q1 of 2015.

Recently, milestone goals and their associated target completion dates have been adjusted to align to potential customer demands. Mr. Peter Copetti, Executive Chairman and Interim CEO noted: “It is important for us to remain flexible in setting design targets to the market. The Company is focused on delivering to its potential customers the technology nodes that will enable them to leapfrog their competition. Our “Lab-to-Fab” transition and our new 40-nm target node will deliver just that: a roadmap for integrating electrical and optical capabilities, performance and power efficiency.”

Operational Updates

The Company is anticipating delivery of the 40-nm PET Process Design Kits (PDKs) by the end of the year. The Company is using Synopsys TCAD tools and services to develop the PET and POET PDKs. PDKs are used by 3rd party chip developers to create IP libraries that would be used to implement System on Chip (SoC) integrated circuits. Availability of the PDKs will enable early evaluation of the performance advantages of POET technology and design of IP required for SoC implementation. Daniel DeSimone, the Company’s Chief Technology Officer noted: “We are encouraged by our progress on the PDK development and our level of collaboration with the Synopsys team. This level of modeling is synergistic to our parallel efforts with our 3rd party foundry on the development of 100-nm and 40-nm process flow.”

The Company’s website and the corporate presentation have been updated to highlight the new targets set forth from the management team that reflect customers and market expectations. The value proposition of the company is strong with the new 40-nm feature size target predicted to operate 4 nodes better in logic performance and 3 nodes better in power consumption compared to Silicon CMOS. The density is expected to be comparable and possibly better, as POET requires less buffering and upsizing of logic cells. The POET process offers the ability to have digital, analog and mixed signals and optical devices on the same die or chip. Those capabilities would allow designs of complex systems and SoC (Systems on a Chip) to deliver innovations and integration that are impossible today with existing processes in the market. This process node also takes advantage of existing and mature manufacturing capabilities already available in the industry.

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POET Technologies Announces Operational, Financial Position, “Lab-to-Fab” Transition, and Milestone Updates

January 8th, 2015

Toronto, ON, and Storrs, CT, January 8, 2015 – POET Technologies Inc. (TSX-V: PTK and OTCQX: POETF) (the “Company”) – developer of the planar opto-electronic technology (“POET”) platform for monolithic fabrication of integrated circuit devices containing both electronic and optical elements on a single semiconductor wafer – today announced key operational, financial position, “Lab-to-Fab” transition, and milestone updates.

Financial Position

“POET enters 2015 in excellent financial shape,” noted Mr. Peter Copetti, Co-Chairman and interim CEO. “Although we spent on outsourcing and capital equipment through 2014, we start the new year with a cash balance of approximately $12.5 million, a 350% increase from a year earlier. This is our strongest cash position as a company and will allow us to take advantage of opportunities in the following year to maximize shareholder value.” In December 2014, the Company also signed a new lease extension with the University of Connecticut (“UCONN”) for a 1-year period which was pre-paid at a significant discount. The new lease includes a possible further two-year extension and provides us the flexibility to transition from Lab to Fab.

Mr. Copetti added: “2014 has been a great year for POET where our transition from “Lab-to-Fab” has begun with many industry Non-Disclosure Agreement (“NDA”) discussions that have been initiated through the work of Mr. Ajit Manocha, our Co-Chairman. Some of our milestones have had to evolve during 2014 because of industry relationship considerations and priorities. These evolving changes have made the updated milestones more significant to the market place. We enter 2015 with financial stability, significant industry relationships, and milestones relevant to the industry collaborators. The Company believes that we are in an excellent position to monetize our process technology.”

“Lab-to-Fab” Transition: 100-nm and 40-nm Scaling Program Update

POET recently reported a contractual effort with a “3rd party foundry” to accelerate the transition from “Lab-to-Fab” of the POET technology to a manufacturing status at the 6” wafer scale. Significant progress has been made towards transfer of critical manufacturing steps to the “3rd party foundry”. This flow will both accelerate and improve quality of results for prototype fabrication and test supporting process flow and design enablement kit development. Efforts in the lab have been geared towards optimization of the self-aligned contacts for the HFET transistors, as well as on optimization of the vertical structure of the devices. Mr. Daniel DeSimone, Chief Technology Officer noted: “We have seen positive improvement in the key figures of merit we test for in our devices. We see further possible improvements and are continuing to work on device and process flow to achieve the highest possible performance.”

In a parallel development at the UCONN lab, a new additional sputter tool was received and accepted. The tool is nearing completion of internal qualification. Deployment of the new tool will drastically reduce prototype fabrication cycle times as well as improve the quality and process control of key films used in the process flow. These will be critical not only to current development, but also necessary for transfer to eventual manufacturing stages.

Milestone Updates

PET Foundation Process Design Kit (“PDK”) targeting 40-nm – Sentaurus modeling (a Synopsys tool) has been performed with new fabrication innovations to achieve controlled scaled device operation. These modeling predictions are guiding and confirming the device prototype development and testing. The PDK milestone has been moved to Q1 2015 so that the release incorporates the latest innovations currently being developed in the UCONN Lab and in parallel with the “3rd party foundry”.

“3rd Party Foundry” 40/100-nm Transfer – This “Lab-to-Fab” effort requires bringing up critical layers manufacturing capability in our “3rd party foundry” which enables more complex test structures. Significant progress has been achieved towards the completion of this milestone. The Company is very close to completing qualification runs for the flow in which the critical layers are performed at our “3rd party foundry”. This new flow will significantly accelerate completion and optimization of development on 100 and 40-nm foundation devices and associated proof of concept optical and electronic circuit structures.

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POET Technologies Announces the Completion of the “3rd Party Foundry” 40/100-nm Transfer Milestone and Corporate Updates

February 10th, 2015

Toronto, ON, and Storrs, CT, February 10, 2015 – POET Technologies Inc. (TSX-V: PTK and OTCQX: POETF) (the “Company”) – developer of the planar opto-electronic technology (“POET”) platform for monolithic fabrication of integrated circuit devices containing both electronic and optical elements on a single semiconductor wafer – today announced the completion of its “3rd party foundry” 40/100-nm transfer milestone. The Company also announced $4 Million in additional capital raised from institutional and accredited shareholders through the exercise of warrants during the month of January 2015, and the resignation of Dr. Adam Chowaniec from its Board.

Completion of Milestone – “3rd Party Foundry” 40/100-nm Transfer

The Company completed its “3rd Party Foundry” 40/100-nm transfer milestone consisting of completing the critical layers of the Transistor Fabrication Process. This flow process will allow the Company to generate more complex prototypes and test structures. As the POET process node size shrinks, this facilitates new industry innovations and furthers development work. This new epitaxial flow process includes new innovations in the POET prototype fabrication process. These innovations were necessary to continue the optimization work of the 100 and 40-nm foundation devices of our technology.

Dan DeSimone, Chief Technical Officer noted: “This is a significant step for our “lab-to-fab” transition where this new flow at our “3rd Party Foundry” accelerates and adds repeatability and quality to our manufacturing process necessary for our next two significant milestones expected at the end of Q1: a 100-nm ring oscillator and a 50 GHz VCSEL.”