Well i didn't see that one coming, um versus nm, jeez you got me.
Still, why would POET tell everybody that their GaAs-based tech can easily be adapted to Silicon-CMOS foundry?
How could they demonstrate that?
Why partner up with a high-volume world-renkowed 3.5um-450nm foundry in the first place?
Could small form factor be of importance in the equation?
Any ideas, techies ?