Wow, what a great post, schnauser! I really appreciate it and especially like what your tech entrepeneur friend said, as well as your last paragraph.

Regarding the current work and the milestones, your post helps a lot to understand where they currently are. I looked up the roadmap in Suresh's presentation of October last year:

We know that the Q1 milestones have been reached, i.e. we have VCSEL, detector, and transistors, though not optimized.

At the THM Suresh presented this picture, showing detector and VCSEL on the same chip, i.e. integrated, but with the transistors still missing:

That is:

• We have the components in principle, but not completely optimized. At least the VCSEL is not yet optimized. I am assuming detector and transistors are already optimized.
• We have the integration in principle (proven by image above), but not optimized.

Currently the VCSEL optimization is on the way. When that is done, the Q2 milestone are achieved, i.e. we have the "functional transmit and receive components" defined as "demonstrate integrate transmit and receive functions, integrated flow with FETs, VCSELs and detectors."

When POET published the presentation, I thought "flow" meant "data flow" through the components, but now I rather believe they meant the "production flow" in the fab.

The Q3 target is to complete the integration: "Tape out first transceiver prototype" defined as "First pass design for 10 Gbps and 25 Gbps transceivers". That is, the Q3 milestone is to have all artifacts completed and ready to go into VCSEL transceiver production (tapeout). Well, Q§ might actually mean early Q4. We'll see.

Here are statements regarding the VCSEL and the integrated VCSEL transceiver from the THM with some passages highlighted by me:

00:25:32– … And the picture here is actually the picture of our detector and VCSEL. So we’re actually making those as an image of what that looks like on the wafer that is sitting out at the back. The intent is that light eventually shines out of the circular dot in terms of the VCSEL and light shines into that dot in terms of the detector. This gives you a sense of what it is that we’re actually building.

00:26:32– It is the first time you can actually put together a VCSEL and a detector sitting right next to each other on the same piece of wafer. That’s kind of what we’ve done. The technology is enabling a functional integration, if you will.

…

00:32:46– In terms of our recent accomplishments – we talked about the process transfer, we are still in the process of completing that, so our goal is to complete and continue and complete that over the next quarter. We did have our results, six-inch wafers, you can see them at the back, we’ve got them testing now. We’ve built integrated VCSELs and detectors that sit right next to each other on the same piece of wafer on the same run. We’re still working through the last pieces of optimization on the VCSEL. But at least on the detector we’ve been able to characterize it and it behaves the way we expected it to behave.

…

00:34:01– All in all I think that part is going well. We still have a little bit of work to do on the VCSEL, which is a little more complex in terms of the process and working through the final kinks with our foundry on resolving that, but, we have fundamentally built these devices sitting right next to each other, which has never been done before. And that’s what the power of the POET technology is, its epitaxy, its uniqueness as conjectured by Dr. Geoff Taylor, that’s what we are trying to do here.

…

00:35:04– … So I think we’re taking it one step at a time: We’ve got to build the detector, we’ve got to build the VCSEL, and then we’ve got to build the transistors. Once they’re all built then you can put any system together in terms of the design, so it’s kind of a stepwise process ensuring everything is manufacturable.

…

01:24:48–Q:At the last news release we were talking about a functional prototype VCSEL transceiver by the end of the second quarter. Is that timeline still in effect?

01:24:58–Suresh Venkatesan:Oh, a full-fledge transceiver, I mean, the plan is for the end of the year. I think we talked about integrated VCSELs and detectors in the second quarter, and I think we are on plan to do that. You know, we did take, I think as you mentioned, at our last conference call, and also had it in our MD&A release. This whole Anadigics to Wavetek move, it has set us back – we had to transition foundry as Anadigics got acquired, and we got into that. We’ve been trying to catch up, and I think, sometimes we make faster progress than others. Our goal is to try to meet all the milestones that we’ve committed to. There are a little bit more headwinds than we would have expected because of this transition, with, you know, lose a few months in that, but I think we’re recovering more, the devices are starting to look like we wanted them to look.

01:25:55– The epitaxy, to me, that’s the most important thing, has been solved. Because, look, the magic is in the epitaxy, if you don’t get that right, you don’t get anything right. The processing sequences are tuned for the factory. We spent a lot of time tooling it at Anadigics and now we have to redo all that work, because they have different tools, different equipment. But that is engineering, it is not innovation, it just takes time, and that’s what we’re working on. But I’m confident we’ll be able to get there, whether it’s going to be exactly in June or a few weeks here or there. I don’t see any challenges other than being focused 100 percent. Subhash was there last week working with Wavetek on this.

01:26:44–Ajit Manocha:I just want to echo one comment Suresh has made, and I think this is for the future also. When we say that we will have this milestone by Q2, it is our intent always to make it happen with you. But this is all science and engineering. If we know how it works, we have the recipe, then we can deliver it. We are developing recipes. So with the detector announcement was made; the VCSEL is there, but it is just not fully optimized. That’s why it is in the presentation that we are trying to optimize the VCSEL.

01:27:14– So now when you start the process from, again, starting with new wafers, by the time it finishes, it may not happen by June 30th, but it doesn’t mean we are going to miss the milestones. But I want you to just have the mindset here that when we say Q2, [it means] plus/minus two weeks. It’s not plus/minus quarters.

01:27:33– Also, just remember, we go from point A to point B. Sometimes we know there’s a straight path, and we say, okay, we’ve got some hurdles and we did a left turn and another left turn and we get there. So it takes a little longer but that’s sounds of science. I’ve been doing that in my life from the Bell Lab days. We think we’re going to make this happen in three months and sometimes it takes nine months, but the beauty of that is, sometimes it takes more time, while we’re making those turns you find some new things in science and that becomes additional applications. So there’s some gives and takes, but that’s what I’m just trying to say, if you say „Oh, my gosh, you promised Q2“, it is not going to be Q2 2017, it’ll be Q3 2016, but it will happen.