Aiming to become the global leader in chip-scale photonic solutions by deploying Optical Interposer technology to enable the seamless integration of electronics and photonics for a broad range of vertical market applications

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1 wafer x 2000 chips(estimated chips on a wafer).

That's with 100% yield of course. Which leads me to wonder (since this is not my field): are each of those 2000 chips tested AFTER they are cut apart, or is there some ingenious way to test their veracity simultaneously, while the wafer is still intact? and is that even a desirable way to test, if it's possible that the separation process could potentially damage a functional chip?

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